IET Computers & Digital Techniques (IET COMPUT DIGIT TEC)

Publications in this journal

• Article: Advanced calibration techniques for high-speed source-synchronous interfaces

  F. Plessas, A. Alexandropoulos, S. Koutsomitsos, E. Davrazos, M. Birbas
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  ABSTRACT: Advanced and dynamic calibration techniques for maximising the link performance of parallel source-synchronous interfaces are introduced and demonstrated in this study, using as a case study a 533-MHz DDR2 SDRAM memory interface implemented in 90-nm standard complementary metal-oxide-semiconductor (CMOS), whereas most of them have been validated at 800-MHz too. A novel dynamic strobe masking system (DSMS) has also been employed which, in contrast to traditional techniques, adjusts dynamically the length of the masking signal in real time, based on the incoming strobe. Furthermore, optimal data capture is achieved by employing a fast bit-deskew calibration engine, while also a novel I/O calibration scheme is included. Post-layout simulation results demonstrate that the dynamic calibration and skew compensation techniques employed improve the timing margin while providing advanced robustness over process, voltage and temperature variations.
  IET Computers & Digital Techniques 10/2011;
• Source

  Available from: sbu.ac.ir

  Article: Improving the speed of decimal division

  A. Kaivani, A. Hosseiny, G. Jaberipur
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  ABSTRACT: The authors study previous major contributions to digit recurrence decimal division hardware and focus on techniques for improving the performance of quotient digit selection (QDS) as the most complex part. In particular, Design D1 uses the digit set [-5, 5] for quotient digits. Another design (D2) uses mixed binary/decimal carry-save manipulation of the few most significant digits of partial remainders. Motivated by successful combined arithmetic algorithms such as hybrid adders, the authors offer a decimal division scheme that takes advantage of the best design options of D1 and D2 with due modifications that significantly enhance the division speed. In particular, they configure the architectures of QDS and partial remainder computation paths in favour of reduced balanced latencies of both. Furthermore, they remove the rounding cycle by cost-free auto-rounding, which is an exclusive advantage of the digit set [-5, 5]. The authors of D1 and D2 have used logical effort (LE) and circuit synthesis to evaluate their dividers, respectively. Therefore for a fair comparison, the authors evaluate the proposed design (D3) with both methods. The LE-based D3/D1 comparison shows 21- more speed at the cost of 6- more area, whereas the synthesis-based D3/D2 comparison results in 46- less latency and 23- less area.
  IET Computers & Digital Techniques 10/2011;
• Article: Ranking of input cubes based on their lingering synchronisation effects and their use in random sequential test generation

  I. Pomeranz, S.M. Reddy
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  ABSTRACT: The authors define the notion of a lingering synchronisation effect. Such an effect occurs when a primary input cube (an incompletely specified primary input vector) determines the state of a circuit for several time units after it is applied. A primary input cube with a lingering synchronisation effect may prevent certain faults from being detected when it appears repeatedly in a test sequence. It should therefore be avoided when the goal is to achieve a high fault coverage. The authors demonstrate that benchmark circuits have primary input cubes with small numbers of specified values (typically one or two), which have lingering synchronisation effects. In some cases, the synchronisation effects linger for large numbers of time units. The authors define a ranking of primary input cubes based on the severity of their lingering synchronisation effects. They describe a random test generation process that avoids primary input cubes with lingering synchronisation effects, and achieves high fault coverage for benchmark circuits. The test generation process uses the severity of the lingering synchronisation effects of the primary input cubes to decide on the ones it should avoid.
  IET Computers & Digital Techniques 10/2011;
• Article: Variability compensation for full-swing against low-swing on-chip communication

  G. Paci, D. Bertozzi, L. Benini
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  ABSTRACT: Adaptive body bias (ABB) and adaptive supply voltage (ASV) are effective methods for post-silicon tuning to reduce variability on generic combinational circuits or microprocessor circuit sub-blocks. We focus in this work on global point-to-point interconnects, which are evolving into complex communication channels with drivers and receivers, in an attempt to mitigate the effects of reverse scaling and reduce power. The characterisation of the performance spread of these links and the exploration of effective and power-aware compensation techniques for them is becoming a key design issue. This work compares the effectiveness of ABB against ASV when put at work on two on-chip point-to-point link architectures: a traditional full-swing and a low-swing signalling scheme for low-power communication. This work provides guidelines for the post-silicon variability compensation of these communication channels, while considering realistic layout effects. In particular, the implications of cross-coupling capacitance on the effectiveness of variability compensation are analysed in this work.
  IET Computers & Digital Techniques 10/2011;
• Source

  Available from: utah.edu

  Article: History-aware, resource-based dynamic scheduling for heterogeneous multi-core processors

  A.Z. Jooya, A. Baniasadi, M. Analoui
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  ABSTRACT: The authors introduce a history-aware, resource-based dynamic (or simply HARD) scheduler for heterogeneous chip multi-processors (CMPs). HARD relies on recording application resource utilisation and throughput to adaptively change cores for applications during runtime. The authors show that HARD can be configured to achieve both performance and power improvements and compare HARD to an alternative dynamic scheduler and a static scheduler to provide better understanding.
  IET Computers & Digital Techniques 08/2011;
• Article: Field programmable gate array-based acceleration of shortest-path computation

  G.R. Jagadeesh, T. Srikanthan, C.M. Lim
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  ABSTRACT: There exist several practical applications that require high-speed shortest-path computations. In many situations, especially in embedded applications, an field programmable gate array (FPGA)-based accelerator for computing the shortest paths can help to achieve high performance at low cost. This study presents an FPGA-based distributed architecture for solving the single-source shortest-path problem in a fast and efficient manner. The proposed architecture is based on the Bellman-Ford algorithm adapted to facilitate early termination of computation. One of the novelties of the architecture is that it does not involve any centralised control and the processing elements (PEs), which are identical in construction, operate in perfect synchronisation with each other. The functional correctness of the design has been verified through simulations and also in actual hardware. It has been shown that the implementation on a Xilinx Virtex-5 FPGA is more than twice as fast as a software implementation of the algorithm on a high-end general-purpose processor that runs at an order-of-magnitude faster clock. The speed-up offered by the design can be further improved by adopting an interconnection topology that maximises the data transfer rate among the PEs.
  IET Computers & Digital Techniques 08/2011;
• Article: State assignment for sequential circuits using multi-objective genetic algorithm

  B.A. Al Jassani, N. Urquhart, A.E.A. Almaini
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  ABSTRACT: In this study, a new approach using a multi-objective genetic algorithm (MOGA) is proposed to determine the optimal state assignment with less area and power dissipations for completely and incompletely specified sequential circuits. The goal is to find the best assignments which reduce the component count and switching activity. The MOGA employs a Pareto ranking scheme and produces a set of state assignments, which are optimal in both objectives. The ESPRESSO tool is used to optimise the combinational parts of the sequential circuits. Experimental results are given using a personal computer with an Intel CPU of 2.4 GHz and 2 GB RAM. The algorithm is implemented using C and fully tested with benchmark examples. The experimental results show that saving in components and switching activity are achieved in most of the benchmarks tested compared with recent published research.
  IET Computers & Digital Techniques 08/2011;
• Article: Fault model and test procedure for phase change memory

  M.G. Mohammad
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  ABSTRACT: Chalcogenide-based phase change memory (PCM) is a type of non-volatile memory that will most likely replace the currently widespread flash memory. Current research on PCM targets the integration feasibility, as well as the reliability of such memory technology into the currently used complementary metal oxide semiconductor (CMOS) process. Such studies identified special failure modes, known as disturbs, as well as other PCM specific faults. In this study, the authors identify these failures, analyse their behaviours and develop fault primitives/models that describe these faults accurately and effectively. In addition, the authors propose an efficient test algorithm, called March-PCM, to test for these faults and compare its performance to some previously developed test algorithms.
  IET Computers & Digital Techniques 08/2011;
• Article: Editorial - Selected papers from the 16th IEEE International Symposium on Asynchronous Circuits and Systems

  K.S. Stevens, A.(. Yakovlev
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  ABSTRACT: Asynchronous designs employ handshaking to perform communication and data transfer between elements in a system. This method was employed in computer architecture as early as the 1950's. Much has changed since those early days. Rather than design with vacuum tubes and discreet devices, current technology enables designs that can have billions of transistors with 32 nm feature sizes. Asynchronous design technology has likewise advanced. The International Symposium on Asynchronous Circuits and Systems (ASYNC) is the premier forum covering recent technological advances in this area of research. This annual conference brings together researchers and industry experts from around the world to discuss a broad range of topics covering all aspects of asynchronous design and related emerging technologies.
  IET Computers & Digital Techniques 08/2011;
• Source

  Available from: polito.it

  Article: Half-buffer retiming and token cages for synchronous elastic circuits

  M.R. Casu
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  ABSTRACT: Synchronous elastic circuits borrow the tolerance of computation and communication latencies from the asynchronous design style. The datapath is made elastic by turning registers into elastic buffers and adding a control layer that uses synchronous handshake signals and join/fork controllers. Join elements are the objective of two improvements discussed in this study. Half-buffer retiming allows the creation of input queues by relocating one of the latches of the elastic buffer which follows the join controller. Token cages improve the performance of join controllers that use the early-evaluation firing rule. Their effect on throughput is discussed by means of examples representative of typical topologies, simulations with synthetic benchmarks and a realistic microarchitecture. Area and power costs of the control logic and the possible impact on the datapath are evaluated, based on the results of logic synthesis experiments on a 45 nm CMOS technology.
  IET Computers & Digital Techniques 08/2011;
• Article: Blur identification with assumption validation for sensor-based video reconstruction and its implementation on field programmable gate array

  M.E. Angelopoulou, C.-S. Bouganis, P.Y.K. Cheung
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  ABSTRACT: Restoration methods, such as super-resolution (SR), largely depend on the accuracy of the point spread function (PSF). PSF estimation is an ill-posed problem, and a linear and uniform motion is often assumed. In real-life systems, this may deviate significantly from the actual motion, impairing subsequent restoration. To address the above, this work proposes a dynamically configurable imaging system that combines algorithmic video enhancement, field programmable gate array (FPGA)-based video processing and adaptive image sensor technology. Specifically, a joint blur identification and validation (BIV) scheme is proposed, which validates the initial linear and uniform motion assumption. For the cases that significantly deviate from that assumption, the real-time reconfiguration property of an adaptive image sensor is utilised, and the sensor is locally reconfigured to larger pixels that produce higher frame-rate samples with reduced blur. Results demonstrate that once the sensor reconfiguration gives rise to a valid motion assumption, highly accurate PSFs are estimated, resulting in improved SR reconstruction quality. To enable real-time reconstruction, an FPGA-based BIV architecture is proposed. The system's throughput is significantly higher than 25 fps, for frame sizes up to 1024 × 1024, and its performance is robust to noise for signal-to-noise ratio (SNR) as low as 20 dB.
  IET Computers & Digital Techniques 08/2011;
• Article: Fault tolerance for nanotechnology devices at the bit and module levels with history index of correct computation

  Y. Dotan, N. Levison, D. Lilja
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  ABSTRACT: Future nano-scale devices are expected to shrink to ever smaller dimensions, to operate at low voltages and high frequencies, to be more sensitive to environmental influences and to be characterised by high dynamic fault rates and defect densities. Fundamentally new fault-tolerant architectures are required in order to produce reliable systems that will operate correctly. Simple replication of micro-architecture blocks will no longer suffice, as all replicated blocks will have faults. The history index of correct computation (HICC) is examined in a recursive and non-recursive fault-tolerant approach at the bit and module levels to identify reliable blocks on-the-fly and forward their computation results, while ignoring results from unreliable blocks. Simulation results show that recursive and non-recursive HICC offers the best resilience to faults when faults are non-uniformly distributed among redundant blocks. A correct computation rate of 99% is achieved using the recursive HICC when decision units at the bit and module levels are fault free, despite an average fault injection rate of 20% compared to a 68% correct computation rate for the recursive triple modular redundancy voter. When faults are injected everywhere in the design, the non-recursive HICC supports the best correct computation percentage. The effect of circuit size and history indices are also examined and discussed.
  IET Computers & Digital Techniques 08/2011;
• Article: Energy-minimum sub-threshold self-timed circuits using current-sensing completion detection

  O.C. Akgun, J.N. Rodrigues, J. Sparsø
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  ABSTRACT: This study addresses the design of self-timed energy-minimum circuits, operating in the sub-V_T domain and a generic implementation template using bundled-data circuitry and current sensing completion detection (CSCD). Furthermore, a fully decoupled latch controller was developed, which integrates with the current-sensing circuitry. Different configurations that utilise the proposed latch controller are highlighted. A contemporary synchronous electronic design automation tools-based design flow, which transforms a synchronous design into a corresponding self-timed circuit, is outlined. Different use cases of the CSCD system are examined. The design flow and the current-sensing technique are validated by the implementation of a self-timed version of a wavelet-based event detector for cardiac pacemaker applications in a standard 65 nm CMOS process. The chip was fabricated and verified to operate down to 250 mV. Spice simulations indicate a gain of 52.58 in throughput because of asynchronous operation. By trading the throughput improvement, energy dissipation is reduced by 16.8 at the energy-minimum supply voltage.
  IET Computers & Digital Techniques 08/2011;
• Article: Integration schemes and enabling technologies for three-dimensional integrated circuits

  K.N. Chen, C.S. Tan
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  ABSTRACT: Various integration schemes and key enabling technologies for wafer-level three-dimensional integrated circuits (3D IC) are reviewed and discussed. Stacking orientations (face up or face down), methods of wafer bonding (metallic, dielectric or hybrid), formation of through-silicon via (TSV) (via first, via middle or via last) and singulation level (wafer-to-wafer or chip-to-wafer) are options for 3D IC integration schemes. Key enabling technologies, such as alignment, Cu-Cu bonding and TSV fabrication, are described as well. Improved performance, such as lower latency and higher bandwidth, lower power consumption, smaller form factor, lower cost and heterogeneous integration of disparate functionalities, are made possible in the next generation of electronics products with the realisation of 3D IC.
  IET Computers & Digital Techniques 06/2011;
• Article: Reconfigurable five-layer three-dimensional integrated memory-on-logic synthetic aperture radar processor

  T. Thorolfsson, N. Moezzi-Madani, P.D. Franzon
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  ABSTRACT: In this study, the authors present a floating-point synthetic aperture radar processor that achieves a power efficiency of 18.0 mW/GFlop in simulation through the use of three-dimensional (3D) integration and reconfiguration of the data path. The reconfiguration reduces the number of arithmetic units required in every processing element (PE) from 24 down to 10. The processor uses a 3D integrated memory that reduces the memory power consumption by 70 when compared to a 2D memory. The system processes a SAR image using a two-tier 3D integrated PE, which when compared to an equivalent 2D PE decreases the power consumed in the interconnect of each PE by 15.5 and the footprint by 49.2 , and allows the PE to operate 7.1 faster in simulation. Additionally, by using 3D integration in the memory one can reduce the power consumption of the memory by 70 . Furthermore, the authors show how the 3D aspects of the processor can be realised by using 2D tools, when used in conjunction with the proposed through-silicon via assignment algorithm.
  IET Computers & Digital Techniques 06/2011;
• Article: Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation

  X. Dong, X. Wu, Y. Xie, Y. Chen, H. Li
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  ABSTRACT: Magnetic random access memory (MRAM) has been considered as a promising memory technology because of its attractive properties such as non-volatility, fast access, zero standby leakage and high density. Although integrating MRAM with complementary metal-oxide-semiconductor (CMOS) logic may incur extra manufacturing cost because of the hybrid magnetic-CMOS fabrication process, it is feasible and cost-effective to fabricate MRAM and CMOS logic separately and then integrate them using 3D stacking. In this work, we first studied the MRAM properties and built an MRAM cache model in terms of performance, energy and area. Using this model, we evaluated the impact of stacking MRAM caches atop microprocessor cores and compared MRAM against its static random access memory (SRAM) and dynamic random access memory (DRAM) counterparts. Our simulation result shows that MRAM stacking can provide competitive instruction-per-cycle (IPC) performance with a large reduction in power consumption.
  IET Computers & Digital Techniques 06/2011;
• Article: Thermal-electrical co-optimisation of floorplanning of three-dimensional integrated circuits under manufacturing and physical design constraints

  A. Jain, S.M. Alam, S. Pozder, R.E. Jones
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  ABSTRACT: Although the stacking of multiple strata to produce three-dimensional (3D) integrated circuits (ICs) improves interconnect length and hence reduces power and latency, it also results in the exacerbation of the thermal management challenge owing to the increased power density. There is a need for design tools to understand and optimise the trade-off between electrical and thermal design at the device and block levels. This study presents results from thermal-electrical co-optimisation for block-level floorplanning in a multi-die 3D IC under various manufacturing and physical design constraints. A method for temperature computation based on linearity of the governing energy equation is presented. This method is combined with previously reported electrical delay models for 3D ICs to simultaneously optimise both the maximum temperature and the interconnect length. It is shown that co-optimisation of thermal and electrical objectives results in a floorplan that is attractive from both perspectives. Physical design constraints because of cost-effective 3D manufacturing such as using fully or partly identical dies using reciprocal design symmetry (RDS), differentiated technology in each die and thinned die/wafer are discussed and their impact on the thermal-electrical co-optimisation is investigated. In some cases, the cheapest manufacturing choice, such as using identical die, for each layer may not result in optimal thermal and electrical design. Results presented in this work highlight the need for thermal and electrical co-design in multi-strata microelectronics, and for reconciling manufacturing and design considerations in order to develop practical design tools for 3D ICs.
  IET Computers & Digital Techniques 06/2011;
• Article: Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration

  T. Karnik, D. Somasekhar, S. Borkar
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  ABSTRACT: Promise of form-factor reduction and hybrid process integration by three-dimensional (3D)-stacked integrated circuits (3DICs) has spurred interest in both academia and industry. In this study, through-silicon-via (TSV)-based 3D integration is discussed from a microprocessor centric view. The authors present the challenges faced by technology scaling and provide 3D integration as a possible solution. The applications for 3DICs are discussed with details of a few prototypes. The issues and challenges associated with 3D integration technologies are also addressed. TSV-based 3D integration technology will allow integration of diverse functionality to realise energy-efficient and affordable compact systems that will continue to deliver higher performance.
  IET Computers & Digital Techniques 06/2011;
• Article: Three-dimensional integrated circuits implementation of multiple applications emphasising manufacture reuse

  C.-M. Hung, Y.-L. Lin
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  ABSTRACT: The authors propose a platform-based approach called Chipsburger for three-dimensional integrated circuits (3D IC) implementation of multiple electronics systems. The authors emphasise manufacturing reuse to lower the total non-recurring engineering and mass-production cost of 3D chips for multiple applications. Given a set of applications each employing a set of IPs and needing a certain amount of mass-production volume, the author's target 3D IC stack consists of platform dies and customised dies. Platform dies can be manufactured in large volume at low unit cost and used in multiple applications; Customised dies for individual application, on the other hand, will be smaller and easier to implement, as certain functionality has been allocated to the platform dies. The authors have developed a 3D IC cost model to evaluate platform-die configurations and compare the cost benefit of Chipsburger with that of either one 2D system-on-a-chip or 3D IC per application. The authors also develop a platform generator program for finding an optimised platform for a set of applications. Experimental results over industrial examples indicate that Chipsburger is indeed cost-effective for certain range of volume requirements.
  IET Computers & Digital Techniques 06/2011;