Circuits and Systems II: Express Briefs, IEEE Transactions on Journal Impact Factor & Information

Publisher: IEEE Circuits and Systems Society; Institute of Electrical and Electronics Engineers, Institute of Electrical and Electronics Engineers

Current impact factor: 1.23

Impact Factor Rankings

2015 Impact Factor Available summer 2016
2014 Impact Factor 1.234
2013 Impact Factor 1.187
2012 Impact Factor 1.327
2011 Impact Factor 1.41
2010 Impact Factor 1.334
2009 Impact Factor 1.32
2008 Impact Factor 1.436
2007 Impact Factor 1.104

Impact factor over time

Impact factor

Additional details

5-year impact 1.55
Cited half-life 7.80
Immediacy index 0.13
Eigenfactor 0.01
Article influence 0.75
Other titles IEEE transactions on circuits and systems. II, Express briefs, Express briefs, Transactions on circuits and systems., Circuits and systems., IEEE transactions on circuits and systems
ISSN 1549-7747
OCLC 54412334
Material type Periodical, Internet resource
Document type Journal / Magazine / Newspaper, Internet Resource

Publisher details

Institute of Electrical and Electronics Engineers

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  • Classification
    ​ green

Publications in this journal

  • Circuits and Systems II: Express Briefs, IEEE Transactions on 10/2015;
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    ABSTRACT: With a real analog bandpass filter (BPF) in the feedback loop, band-limited digital predistortion (DPD) normally uses a narrower bandwidth low-pass filter at baseband to further constrain the bandwidth of the power amplifier (PA) output signal. This discards the nonlinear information at the BPF's roll-off regions. The PA's spectral regrowth at the edge of the BPF is thus unable to be suppressed with the conventional band-limited DPD. To make efficient use of digital-to-analog converter/analog-to-digital converter sampling rate without losing information at the BPF's roll-off regions, this brief proposes a band-divided DPD method, in which the restricted feedback bandwidth is divided into two parts in frequency domain—center and border regions of PA's band-limited output. These two parts are characterized separately using two different basis functions with a band-divided memory polynomial (BDMP) model. It provides higher flexibility in selecting the digital band-limiting filter's bandwidth and also reduces the filter order. The measurement results for a class-AB GaN PA with orthogonal frequency division multiplexing signal of 60-MHz bandwidth have shown the superiority of BDMP DPD over the previous state-of-the-art.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 10/2015; 62(10):922-926. DOI:10.1109/TCSII.2015.2457793
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    ABSTRACT: A 2.4-GHz all-digital phase-locked loop (ADPLL) for Zigbee application is presented. A stochastic time-to-digital converter (STDC) with an edge-interchange circuit (EIC) is proposed. The rising edges of the two input clocks of STDC are cyclically interchanged by EIC, which achieves dynamic element matching and doubles the equivalent number of arbiters in STDC. The frequency resolution of the $LC$-based digitally controlled oscillator is improved by the tiny unit capacitor and the high-speed dithering. The proposed ADPLL has been implemented in a 0.13- $mumbox{m}$ CMOS technology. The measurement results show a 9-mW total power consumption, in which the proposed 1-ps-resolution STDC only consumes 0.9 mW. The in-band and out-band phase noise are −83.0127 dBc/Hz at 10 kHz and −118.95 dBc/Hz at 1 MHz. The root-mean-square jitter and peak-to-peak jitter are 4.6 and 25.7 ps, respectively.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 10/2015; 62(10):917-921. DOI:10.1109/TCSII.2015.2457792
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    ABSTRACT: We propose a new diffusion least-mean-squares algorithm that utilizes adaptive gains in the adaptation stage for the sparse distributed estimation problem. We derive the optimal gains that attain a minimum mean-square deviation and also propose an adaptive gain control method. We provide the mean stability analysis to establish sufficient condition for the algorithm to converge in the mean sense. The algorithm achieves higher convergence speed than the sparsity-constrained algorithms, regardless of the sparsity of the vector of interest.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 10/2015; 62(10):1-1. DOI:10.1109/TCSII.2015.2435631
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    ABSTRACT: This brief presents a novel and efficient design for a Rivest-Shamir-Adleman (RSA) cryptosystem with a very large key size. A new modular multiplier architecture is proposed by combining the fast Fourier transform-based Strassen multiplication algorithm and Montgomery reduction, which is different from the interleaved version of Montgomery multiplications used in traditional RSA designs. Anew modular exponentiation algorithm is also proposed for the RSA design. Applying this method, we have implemented 8K/12K-bit and 48K-bit RSA on application-specific integrated circuit designs. The results show that the proposed method gains more advantage as the key size increases, which matches the complexity analysis. Performance comparisons show that the 48K-bit design, which is applicable for both RSA and fully homomorphic encryption, outperforms the previous works with respect to throughput and efficiency.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 10/2015; 62(10):1-1. DOI:10.1109/TCSII.2015.2458033
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    ABSTRACT: During mass production, bandgap reference failure can cause chip failure, resulting in yield loss. A bandgap reference with robust start-up behavior is therefore needed. In this brief, the issue of multiple operating points is examined, along with a prior art low-voltage current-mode bandgap reference (CMBGR) structure. A CMBGR structure with only two stable operating points is proposed, which can be reliably started up with a very simple pulse generator circuit and a power-up signal. The bandgap reference is implemented in 40-nm technology, achieving a 41.5-ppm/°C nominal temperature coefficient. The current consumption is 40 $mumbox{A}$ and the active area is 0.0094 mm 2.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 10/2015; 62(10):937-941. DOI:10.1109/TCSII.2015.2458044
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    ABSTRACT: A low-leakage body-guarded analog switch (BG-switch) for slow switched-capacitor (SC) circuits is presented. The improvement of accuracy in SC circuits employing BG-switches is demonstrated by comparing their performance with counterparts employing conventionally biased CMOS switches in three applications: sample-and-hold (S/H) amplifier, SC amplifier, and high-voltage drain-extended MOSFET (DEMOS). The leakage currents of BG-switch-enabled circuits are characterized across process variations and different operation voltages in all demonstrated applications. With nominal output voltages at room temperature, the average absolute leakage current of BG-switch-enabled S/H amplifier (12.02 aA), SC amplifier (54.52 aA), and DEMOS (53.71 fA) show leakage current improvement of 21, 28, and 17 dB, respectively, compared with equivalent circuits utilizing transmission gates (TGs). BG-switch-enabled S/H circuits and SC amplifiers with average performance exhibit lower leakage currents up to 100 °C compared with TG-enabled circuits. The demonstrated applications utilizing BG-switches were fabricated in a standard 0.35- $mumbox{m}$ BiCMOS process.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 10/2015; 62(10):947-951. DOI:10.1109/TCSII.2015.2458093
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    ABSTRACT: This brief presents a nonlinearity-cancelation technique in a 0-2 MASH voltage-controlled oscillator (VCO)-based delta-sigma (ΔΣ) analog-to-digital converter (ADC), where the VCO's distortion is substantially mitigated in a power-efficient way. A dual-input VCO-based quantizer topology is also proposed to implement a low-power multiple-input adder and integrator, with nox penalty in terms of nonlinearity. Fabricated in a 40-nm complementary metal-oxide-semiconductor process, a proof-of-concept 0-2 MASH 12-bit ADC prototype achieves a 66.8-dB signal-to-noise and distortion ratio with a 40-MHz bandwidth (BW) and consumes only 4.98 mW. This result extends the figure of merit of the state-of-the-art high-BW (ΔΣ) ADCs to 35 fJ/step.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 10/2015; 62(10):1-1. DOI:10.1109/TCSII.2015.2458111
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    ABSTRACT: The multistage frequency-response masking (FRM) technique is widely used to reduce the complexity of a filter when the transition bandwidth is extremely small. In this brief, a real generalized two-stage FRM filter without any constraint on the subfilters or the interpolation factors was proposed. New principles and equations were deduced to determine the design parameters. The subfilters were then jointly optimized using nonlinear optimization. Experiential results show that when the proposed algorithm obtains different solutions with the conventional algorithm, the solution of the proposed approach is better with less number of filter coefficients and sometimes with lower delay as well than the conventional two-stage FRM, which can lead to a reduced hardware cost in applications.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 10/2015; 62(10):982-986. DOI:10.1109/TCSII.2015.2457794
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    ABSTRACT: Bandwidth mismatch is one of the mechanisms that reduce linearity in time-interleaved analog-to-digital converters (TI-ADCs). Models of bandwidth mismatch have been already proposed in the literature: this brief extends them to subsampling signals, validates them against circuit-level simulations, and investigates their effect on linearity in subsampling applications. The effectiveness of two previously published calibration algorithms for the correction of bandwidth mismatch is shown. The proposed models can thus be used to simulate subsampling TI-ADCs and their calibration algorithms.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 10/2015; 62(10):1-1. DOI:10.1109/TCSII.2015.2458131
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    ABSTRACT: The problem of leader-following consensus in second-order multiagent systems is investigated in this brief, where the data are sampled randomly within a certain known bound and the data transmission is driven by an event-triggered control protocol. A distributed event-triggered control protocol is designed, in which the Zeno behavior is naturally excluded by the strictly positive sampling intervals and the data transmission is largely reduced. Under the proposed protocol, the sufficient condition is derived for assuring the consensus, which declares that the consensus can be achieved if the control gains and the sampling intervals are reasonable. Some numerical examples are provided to demonstrate the effectiveness of the proposed protocol.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 10/2015; 62(10):1007-1011. DOI:10.1109/TCSII.2015.2458036
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    ABSTRACT: This brief proposes a small-area and energy-efficient 12-bit successive approximation analog-to-digital converter (SA-ADC) for CMOS image sensors with a column-parallel readout structure. The proposed SA-ADC, which uses only a 6-bit capacitor digital-to-analog converter (DAC) for residue sampling, reduces the capacitor area to 1/64th of that for the 12-bit capacitor DAC and adopts the scaled reference voltages for 12-bit conversion. It also achieves 88% lower switching energy of the capacitor DAC compared with the 12-bit SA-ADC with split capacitor structure. A foreground digital calibration is employed to compensate for the linearity error caused by the inaccurately scaled reference voltages. A test chip, which has 100 readout channels with the proposed SA-ADC, is fabricated using a 0.18- $mumbox{m}$ CMOS process. The measurement results show that the proposed SA-ADC with the proposed digital calibration has differential nonlinearity (DNL) of −0.8/+1.7 LSB and integral nonlinearity (INL) of −2.3/+2.4 LSB, and without the calibration, it has DNL of −1/+14.9 LSB and INL of −15.8/+12.7 LSB. In addition, a digital correlated double sampling method improves the standard deviation of the readout channel outputs from 62.1 to 1.4 LSB.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 10/2015; 62(10):932-936. DOI:10.1109/TCSII.2015.2457812
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    ABSTRACT: Although class D amplifiers (CDAs) are highly advantageous over their linear amplifier counterparts in terms of power efficiency, their power efficiency remains undesirably low at nominal operation conditions where the output power is $sim$26 dB lower than its peak output power (due to the large crest factor of the audio/speech signal and headroom for adjustment). This is particularly the case for power-critical micropower applications such as hearing instruments. At nominal conditions, we find that the overcurrent protection circuit (for the output stage) is unexpectedly the most power-dissipative block in micropower CDAs. In this brief, we propose a novel ultralow-power overcurrent protection circuit, which features 67% lower power dissipation compared to conventional overcurrent protection circuit without compromising the IC area. To further verify the advantages of the proposed overcurrent protection circuit, an ultralow-power bang–bang CDA is designed. We show that, by employing the proposed overcurrent protection circuit, the power efficiency of the bang–bang CDA is significantly improved from 10.5% to 23.7% for a 64- $Omega$ load and from 1.8% to 4.7% for a 400- $Omega$ load.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 10/2015; 62(10):942-946. DOI:10.1109/TCSII.2015.2458035
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    ABSTRACT: This brief presents a new multistage noise-shaping (MA 4b7 SH) structure that has less hardware by applying partially folded architecture. A folded MASH architecture that exploits adders in half is introduced, and the proposed architecture combines the folded MASH architecture and the conventional MASH architecture. The noise power spectrum of the proposed architecture is mathematically analyzed and the noise-shaping capability of the MASH architecture is preserved.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 10/2015; 62(10):1-1. DOI:10.1109/TCSII.2015.2458034
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    ABSTRACT: This brief presents a design strategy for a neural recording amplifier array with ultralow-power low-noise operation that is suitable for large-scale integration. The topology combines a highly efficient but supply-sensitive single-ended first stage with a shared reference channel and a differential second stage to effect feedforward supply noise cancellation, combining the low power of single-ended amplifiers with improved supply rejection. For a two-channel amplifier, the measurements show a midband gain of 58.7 dB and a passband from 490 mHz to 10.5 kHz. The amplifier consumes 2.85 $mumbox{A}$ per channel from a 1-V supply and exhibits an input-referred noise of 3.04 $mumbox{V}_mathrm{rms}$ from 0.1 Hz to 100 kHz, corresponding to a noise efficiency factor of 1.93. The power supply rejection ratio is better than 50 dB in the passband. The amplifier is fabricated in a 90-nm CMOS process and occupies 0.137 $mbox{mm}^{2}$ of chip area.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 10/2015; 62(10):927-931. DOI:10.1109/TCSII.2015.2457811
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    ABSTRACT: Abstract—In this brief, a high-resolution SAR ADC architecture for biomedical data acquisition is proposed. Filtered LSB segment is employed as a dither to improve the resolution. Theoretical analysis and behavioral simulation show that the error of the MSB segment can be converted into a shaped noise, if the input signal is sufficiently small. The proposed self-dithering technique can be used together with averaging to improve the SNR and the DNL performance. The performance improvement is similar to that of a conventional nonsubtractive scheme using a uniform deterministic dither, but with simplified hardware and reduced computation complexity.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 10/2015; DOI:10.1109/TCSII.2015.2468921