Circuits and Systems II: Express Briefs, IEEE Transactions on (IEEE T CIRCUITS-II )

Publisher: IEEE Circuits and Systems Society; Institute of Electrical and Electronics Engineers

Description

  • Impact factor
    1.33
    Show impact factor history
     
    Impact factor
  • 5-year impact
    1.52
  • Cited half-life
    6.50
  • Immediacy index
    0.21
  • Eigenfactor
    0.02
  • Article influence
    0.87
  • Other titles
    IEEE transactions on circuits and systems. II, Express briefs, Express briefs, Transactions on circuits and systems., Circuits and systems., IEEE transactions on circuits and systems
  • ISSN
    1549-7747
  • OCLC
    54412334
  • Material type
    Periodical, Internet resource
  • Document type
    Journal / Magazine / Newspaper, Internet Resource

Publications in this journal

  • Circuits and Systems II: Express Briefs, IEEE Transactions on 10/2014; 61(10):778-782.
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    ABSTRACT: This brief contributes to the design of computational and reconfigurable structures which exploit the unique threshold-dependent switching response of single memristors and their compositions. A new logic circuit design paradigm, which assumes parallel processing of input signals, is proposed, along with a methodology for the construction of robust programmable composite memristive switches of variable precision. This methodology is applied to the design of memristive computing circuits. A SPICE simulation based validation of the proposed circuits and systems is provided.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 09/2014;
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    ABSTRACT: Higher density of integration and lower power technologies are becoming more sensitive to soft errors caused by radiations. Not only memories and latches are being affected but also combinatorial circuits. Hardening by design techniques based on increasing the amount of charge representing the bit and redundancy techniques have been used over the years. But what happens if the hardening is affected? Who guards the guardians? This work proposes a system that acts as an SET lter and as a check point with self healing properties to prevent SET propagation. This is achieved thanks to feedback using bulk built-in current sensors (BICS).
    Circuits and Systems II: Express Briefs, IEEE Transactions on 09/2014;
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    ABSTRACT: In this brief, a high-order temperature-compensated 0.6-V low-dropout voltage source (LDVS) is realized in standard 0.13- $muhbox{m}$ CMOS technology. The LDVS operates at supply voltages down to 0.75 V and consumes only 39 $muhbox{A}$ while providing up to 100 mA of load current. Gate-to-channel capacitance values of MOSFETs are employed to implement the capacitors, reducing chip area and enabling integration in any inexpensive CMOS technology. The regulation loop is compensated using a combined pole-splitting and feedforward technique, which results in stable operation from a no-load current to 100 mA of full-load current. A temperature-dependent current-driven voltage generator is proposed to suppress the line-voltage sensitivity of the LDVS. To further improve line regulation, a line-voltage compensation circuit is introduced, which lowers the line sensitivity by about three times down to 0.54%/V. With a supply voltage of 1 V and no output filtering capacitor, the mean power-supply rejection is $-$51 and $-$24 dB for 1 and 10 MHz, respectively. The proposed LDVS requires no startup circuit. The 0.1% startup settling time is 73 $muhbox{s}$ with a supply voltage of 0.8 V and a load current of 1 mA. In the temperature range of $-25 ^{circ}hbox{C}$– $,+85 ^{circ}hbox{C}$, it demonstrates a maximum temperature drift of only 32 $hbox{ppm}/^{circ}hbox{C}$.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 06/2014; 61(6):413-417.
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    ABSTRACT: The hysteresis loop pinched at the origin of the v-i characteristic is the well-known fingerprint of the memristor excited by sinusoidal signal. This paper generalizes the present knowledge of the parameters of the pinched hysteresis loop for a periodical zero-DC driving signal described by an odd function of time. The paper concurrently brings new relationships between the parameter vs. state map characteristics, the type of the excitation, and the type of the loop pinching.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2014;
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    ABSTRACT: This brief presents a global-shutter imager readout architecture that allows a dynamic range (DR) of more than 132 dB and a high frame rate. It is based on a stacked technology where the top tier contains the back-illuminated pixel array, and the bottom tier contains the subpixel logic array, which implements the dynamic-range extension by selecting the best integration time for each pixel. Experimental results of a 64 $times$ 64 subpixel array confirm the effectiveness of the proposed method in extending the DR by more than 10 bits. The application of the algorithm to higher array resolutions compromises its effectiveness given the increased column capacitance. As a way out, we propose a novel source-follower-based buffer that reduces the settling time of the subpixel without increasing its size. The performed analysis shows that the sensor can reach 1900 and 375 fps, respectively, at full HD and at 8-K resolutions.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 04/2014;
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    ABSTRACT: Selective filters are obtained by the approximation of the rectangular magnitude. Classic approximation methods employ polynomials or rational functions. Modern methods are based on numerical optimization. The optimization-based approach is effective and gives the designer much freedom. However, the polynomial methods are still attractive because they result in closed-form expressions and simple design procedures. This brief presents a class of low-pass filters that approximate the rectangular magnitude by using the Bernoulli polynomials. The presented filters have equiripple magnitude responses in the lower parts of the passbands, nonequiripple responses at the frequencies approaching the cutoff, and steep transition bands. Furthermore, they have low quality factors of the poles.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 02/2014; PP(99):1-5.
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    ABSTRACT: A novel 1-D sampling method is proposed to calculate 2-D diamond-shaped discrete frequency distributions, which are often treated in the harmonic balance method. The proposed method fills up the entire 2-D discrete frequency plane with diamond-shaped rhombic tiles and makes the number of sampling points equal to that of the necessary frequency components.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(4):269-273.
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    ABSTRACT: This brief investigates a tradeoff between the integral squared error and the peak deviation error for a variable fractional delay (VFD) filter with a coefficient relationship. The integral squared error is minimized subject to additional constraints on the peak deviation error. The problem is solved by utilizing second-order cone programming. In addition, the performance of the VFD filter with discrete coefficients is investigated, in which the filter coefficients are expressed as the sum of power-of-two terms to reduce the filter operations to shifts and adds. Design examples show that the peak deviation error can be significantly reduced from the least squares solution while maintaining approximately the same integral squared error. Similarly, the integral squared error can be significantly reduced from the minimax solution while maintaining approximately the same peak deviation error. Furthermore, the tradeoff filters are less sensitive with respect to quantization than the least squares and minimax solutions.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(1):36-40.
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    ABSTRACT: In this brief, a 1/10-rate bang–bang phase detector (BBPD) using a single edge-tracking clock and a phase interpolator (PI)-based clock and data recovery (CDR) circuit with the proposed BBPD is presented. While a typical 1/ $N$-rate BBPD uses 2 $N$ clocks for data sampling and edge tracking, the proposed 1/ $N$ rate BBPD uses only $N + 1$ clocks, $N$ for data sampling and 1 for edge tracking. The power consumption of the CDR with the proposed 1/ $N$-rate BBPD is decreased. The reduction of the jitter tracking bandwidth of the CDR is compensated by the proposed data-encoding method. The 1/10-rate PI-based CDR with the proposed BBPD is implemented using a 0.18- $muhbox{m}$ CMOS process technology. The bit error ratio of less than $10^{-12}$ is achieved at the effective data rate of 6.93 Gb/s using encoded $2^{31} - 1$ pseudorandom binary-sequence data inputs. The power consumption of the CDR is 29.4 mW at the supply voltage of 1.8 V and the active area is 0.117 $hbox{mm}^{2}$. The effective power efficiency of the CDR is 4.24 mW/Gb/s.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(4):239-243.
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    ABSTRACT: A 10-bit 40-MS/s analog-to-digital converter (ADC) that is suitable for wireless access in vehicular environment applications is introduced. In order to satisfy the severe requirement of a wide range operating temperature under the given constraints, the ADC was simplified by eliminating nonessential building blocks such as reference drivers, a sample-and-hold amplifier (SHA), and level shifters. The proposed internal signal amplification method extends the effective signal range in both multiplying digital-to-analog converter and flash ADC, as well as the error correction range. A new clock generation circuit for a SHA-less pipelined ADC removes the need for a higher frequency external clock. The prototype ADC was fabricated in a 180-nm CMOS process. The ADC core consumes 23.4 mW at 3.3-V/1.8-V supplies. The measured worst differential nonlinearity and integral nonlinearity were $-0.52/!+0.7$ LSB and $-0.86/ !+0.9$ LSB, respectively, at a temperature of $-40 ^{circ} hbox{C}$. The signal-to-noise-and-distortion ratio stayed above 55 dB in the Nyquist condition in a temperature range of $-40 ^{circ}hbox{C}{-}125 ^{circ}hbox{C}$, which is about a 0.5 effective-number-of-bits drop from the room-temperature result.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(1):6-10.
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    ABSTRACT: In this brief, the authors propose time-quantized pseudorandom sampling (TQ-PRS) as a power-saving solution compared with conventional uniform sampling. Due to its ability to reduce replicas' power levels, TQ-PRS reduces the design constraints on receiver components. Applied on the baseband stage of a multistandard radio receiver, TQ-PRS allows decreasing the antialiasing filter order, as well as reducing the sampling frequency. This feature leads to saving up to 30% of baseband power consumption.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(6):443-447.
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    ABSTRACT: Networked predictive control (NPC) is an effective technique to compensate for transmission delays and packet dropout in networked control systems (NCS). By introducing an auxiliary error variable, in this brief, the NCS with NPC is transformed to a coupled switched system. Then, based on the switched system theory and the small gain theorem, a new stability criterion is developed under the restrictions of unstable sampling point rate. As a special case that all switched systems are Schur stable, the proposed criterion is equivalent to existing ones. The proposed stability criterion is much less conservative than existing ones, as shown from both theory and numerical simulations.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(6):453-457.
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    ABSTRACT: A new conjugate symmetric discrete orthogonal transform (CS-DOT)-generating method is proposed. The spectra of the CS-DOT for real input signals are conjugate symmetric so that we only need half memory size to store data. Meanwhile, the proposed CS-DOT also has a radix-2 fast algorithm so that it is suitable for hardware implementation. The CS-DOT generalized the existing transforms such that the discrete Fourier transform (DFT) and the conjugate symmetric sequency-ordered complex Hadamard transform (CS-SCHT) are special cases of the CS-DOT. The CS-DOT-generating method is more systematic and generalized than that of the original CS-SCHT. We can use the same implementation structure but only adjust the twiddle factors to construct the CS-SCHT and DFT so that it is easy to switch the behaviors between these transforms.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(4):284-288.
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    ABSTRACT: Pinning control synchronization of complex networks is a fascinating and hot issue in the field of nonlinear science. However, the existing works are all based on a continuous-time feedback control strategy and assume that each network node can have continuous access to the states of its neighbors. This brief presents a novel distributed event-triggered mechanism for pinning control synchronization of complex networks. The control of nodes is only triggered at their own event time, which effectively reduces the frequency of controller updates compared with continuous-time feedback control. Considering limited communication, the new approach successfully avoids the continuous communication used for calculating the error thresholds in the event-triggered mechanism. In addition, we also develop a new alternative iterative algorithm that can further reduce the consumption of computing and communication resources to some extent. Finally, simulation results show the effectiveness of the proposed approaches and illustrate the correctness of the theoretical results.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(7):541-545.
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    ABSTRACT: This brief presents a convergence analysis and simulation for a new algorithm intended for use in systems with an output power constraint. For example, in an active noise control system that generates an antinoise output to destructively cancel the noise source, we impose the additional requirement of limiting the maximum output power level to prevent system overdrive. The result is a computationally efficient algorithm that allows an explicit power level to be set.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(5):364-367.
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    ABSTRACT: Key blocks used for embedded nor Flash memory are introduced in this brief, including a novel sourceline (SL) voltage compensation circuit and a wordline (WL) voltage-generating system. The SL voltage compensation circuit controls the output voltage of the charge pump according to the number of cells to be programmed with data “0” to compensate the IR drop on the SL decoding path. Thus, a stable SL voltage is obtained and high program efficiency with low program disturb is realized. In order to get low power consumption in standby mode and high speed in active mode, a high-performance WL voltage-generating system has been proposed. A 1.8-V 64 $times$ 32 kb embedded nor Flash memory employing the two techniques has been developed based on a GSMC 0.18- $muhbox{m}$ 4-poly 4-metal CMOS process. Average standby current of the embedded Flash memory IP circuit less than 0.3 $muhbox{A}$ is achieved at 1.8 V and 25 $^{circ}hbox{C}$.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(9):691-695.
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    ABSTRACT: A 13.5-mW 10-Gb/s four-level pulse-amplitude modulation (4-PAM) serial link transmitter is presented. To improve the power efficiency, a voltage-mode 4-PAM driver is proposed. It consists of voltage-scaled pull-up and pull-down networks, instead of conventional current switching networks. Not employing a tail current source, the proposed 4-PAM driver achieves the higher output voltage swing and lower power dissipation than conventional 4-PAM drivers. As a result, the proposed 4-PAM transmitter implemented in a 0.13- $muhbox{m}$ CMOS process achieved 10-Gb/s data rate with only 13.5-mW power dissipation.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(9):646-650.