Circuits and Systems II: Express Briefs, IEEE Transactions on Journal Impact Factor & Information

Publisher: IEEE Circuits and Systems Society; Institute of Electrical and Electronics Engineers, Institute of Electrical and Electronics Engineers

Journal description

Current impact factor: 1.19

Impact Factor Rankings

2015 Impact Factor Available summer 2015
2013 / 2014 Impact Factor 1.187
2012 Impact Factor 1.327
2011 Impact Factor 1.41
2010 Impact Factor 1.334
2009 Impact Factor 1.32
2008 Impact Factor 1.436
2007 Impact Factor 1.104

Impact factor over time

Impact factor
Year

Additional details

5-year impact 1.52
Cited half-life 6.50
Immediacy index 0.21
Eigenfactor 0.02
Article influence 0.87
Other titles IEEE transactions on circuits and systems. II, Express briefs, Express briefs, Transactions on circuits and systems., Circuits and systems., IEEE transactions on circuits and systems
ISSN 1549-7747
OCLC 54412334
Material type Periodical, Internet resource
Document type Journal / Magazine / Newspaper, Internet Resource

Publisher details

Institute of Electrical and Electronics Engineers

  • Pre-print
    • Author can archive a pre-print version
  • Post-print
    • Author can archive a post-print version
  • Conditions
    • Author's pre-print on Author's personal website, employers website or publicly accessible server
    • Author's post-print on Author's server or Institutional server
    • Author's pre-print must be removed upon publication of final version and replaced with either full citation to IEEE work with a Digital Object Identifier or link to article abstract in IEEE Xplore or replaced with Authors post-print
    • Author's pre-print must be accompanied with set-phrase, once submitted to IEEE for publication ("This work has been submitted to the IEEE for possible publication. Copyright may be transferred without notice, after which this version may no longer be accessible")
    • Author's pre-print must be accompanied with set-phrase, when accepted by IEEE for publication ("(c) 20xx IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.")
    • IEEE must be informed as to the electronic address of the pre-print
    • If funding rules apply authors may post Author's post-print version in funder's designated repository
    • Author's Post-print - Publisher copyright and source must be acknowledged with citation (see above set statement)
    • Author's Post-print - Must link to publisher version with DOI
    • Publisher's version/PDF cannot be used
    • Publisher copyright and source must be acknowledged
  • Classification
    ​ green

Publications in this journal

  • [Show abstract] [Hide abstract]
    ABSTRACT: Devices that exhibit resistive switching are promising components for future nanoelectronics with applications ranging from emerging memory to neuromorphic computing and biosensors. In this brief, we present an algorithm for identifying switchable devices, i.e., devices that can be programmed in distinct resistive states and that change their state predictably and repeatedly in response to input stimuli. The method is based on extrapolating the statistical significance of difference in between two distinct resistive states as measured from devices subjected to standardized bias protocols. The test routine is applied on distinct elements of 32 32 resistive-random-access-memory (RRAM) crossbar arrays and yields a measure of device switchability in the form of a statistical significance -value. Ranking devices by -value shows that switchable devices are typically found in the bottom 10% and are therefore easily distinguishable from nonfunctional devices. Implementation of this algorithm dramatically cuts RRAM testing time by granting fast access to the best devices in each array, as well as yield metrics.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 07/2015; 62(7):1-1. DOI:10.1109/TCSII.2015.2415276
  • [Show abstract] [Hide abstract]
    ABSTRACT: This brief presents a dynamic slew enhancement technique for improving the transient response in an adaptively biased low-dropout regulator. This is done by introducing FAST and SLOW paths in an adaptive bias loop. The FAST path injects a quick momentary current during a low-to-high load transient, whereas the SLOW path keeps the current large during a high-to-low load step. The dynamic current shoots up to quite a high level as it is combined with adaptive biasing. When the proposed technique is implemented in the 0.18- CMOS technology, the experimental results show the effective reduction in the undershoot (67%) and the overshoot (66.7%) while maintaining a low quiescent current of 1.1 . The settling times during 0–50-mA and 50–0-mA load transients are improved by 74% and 99.9%, respectively.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 07/2015; 99(7). DOI:10.1109/TCSII.2015.2415311
  • [Show abstract] [Hide abstract]
    ABSTRACT: With the Internet highly developed, complex communication networks are now facing the dilemma of how to use limited resources to achieve the best communication performances. In this brief, we study the resource allocation from a more comprehensive perspective where both allocating the capacities of networks and distributing the rates of traffic flows are considered. We build an optimization problem to optimize the resource allocation and maximize the network utility at the same time. Moreover, we design an iterative algorithm to find the optimal solution. The convergence of this algorithm is supported by theoretical proofs and simulation results. Our work may give insights to the plan of resource allocation in future communication networks.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 07/2015; 62(7):1-1. DOI:10.1109/TCSII.2015.2404220
  • [Show abstract] [Hide abstract]
    ABSTRACT: Level shifters (LS) are crucial interface circuits for multisupply voltage designs, and it is challenging to achieve both robust and efficient level conversion from subthreshold to aforementioned threshold. In this brief, we propose two circuit techniques for a novel subthreshold LS with wide conversion range. First, we introduce a novel LS circuit with NMOS-diode-based current limiter for current contention reduction to achieve robust and efficient level conversion. Second, we explore the inverse narrow width effect to increase the drivability of the pull-down devices for delay reduction. When implemented in a commercial 65-nm MTCMOS process, the proposed LS achieves robust conversion from deep subthreshold (sub-100 mV) to nominal supply voltage (1.2 V). For the target conversion from 0.3 to 1.2 V, the proposed LS shows on average 25.1-ns propagation delay, 30.7-fJ energy efficiency, and 2.5-nW leakage power across 25 test chips.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 07/2015; 62(7):1-1. DOI:10.1109/TCSII.2015.2406354
  • [Show abstract] [Hide abstract]
    ABSTRACT: A technique is developed for representation of any arbitrary linear network as a feedback system. It is based on the fundamental feedback model introduced by Black for systems constituted by unilateral two-port networks. The application of the model is extended to circuits consisting of bilateral two-ports. The system's feedback loop gain for any of the four possible feedback configurations is expressed in terms of parameters of the constituent two-ports connected in cascade. An example is given to illustrate the benefits of the developed technique.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 07/2015; 62(7):1-1. DOI:10.1109/TCSII.2015.2415712
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this brief, an energy-efficient time-to-digital converter (TDC) using a hybrid of time- and voltage-domain circuits is presented. The proposed TDC operates in two steps, i.e., first in the time domain by using a delay-line TDC and then in the voltage domain by using a successive-approximation-register analog-to-digital converter. The time residue of the first stage is converted to voltage by using a switch-based time-to-voltage converter (TVC) that eliminates the need for a current source with large output impedance. To improve the linearity of the proposed TVC, pseudodifferential time-domain signaling is presented. A prototype chip fabricated in the 65-nm CMOS achieves 630 fs of time resolution at 120 megasamples/s while consuming 3.7 mW from a 1.2-V supply. The figure of merit is 244 fJ/conversion-step, which is the best among the recently published high-speed TDCs.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 07/2015; 62(7):1-1. DOI:10.1109/TCSII.2015.2415631
  • [Show abstract] [Hide abstract]
    ABSTRACT: Although segmented voltage-mode digital-to-analog converters (DACs) have been widely used for high-precision DACs in static applications, its code-dependent reference current induces a code-dependent drop through the reference and ground wires, imposing a limitation on the linearity performance. To alleviate this problem, this brief proposes a simple way to compute the reference current and compensate it via a low-resolution auxiliary DAC controlled by a computational block. A (4 12)-bit segmented voltage-mode DAC with the proposed technique is designed and simulated in a 0.6- CMOS process. The SPICE simulation shows a six-time reduction of the integral nonlinearity error from the code-dependent reference current, greatly relaxing the requirement on the reference and ground distribution paths design. Compared with the conventional way of adding high-quality reference and ground buffers on chip, the proposed technique is estimated to take up 1/3 area and consume 1/5 power. With the scaling of the technology, the proposed technique becomes more competent, for 60% area comes from the purely digital computational block. Furthermore, for multichannel DACs, the computational block can be shared among channels if time multiplexing is allowed.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 07/2015; 62(7):1-1. DOI:10.1109/TCSII.2015.2406351
  • [Show abstract] [Hide abstract]
    ABSTRACT: The use of time-selective sampling is presented as a way to significantly reduce the effect of large interferers on the sensitivity of receivers operating in a crowded spectrum. The concept assumes a discrete-time analog front end, where large distorted samples are discarded and small undistorted samples are retained for use in estimating the desired message signals. Since the retained samples are not uniform in time, signal processing is a challenge. The signal processing is described in cases in which 1) the frequencies of the interferers are known and 2) the frequencies are not known.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 07/2015; 62(7):1-1. DOI:10.1109/TCSII.2015.2415711
  • [Show abstract] [Hide abstract]
    ABSTRACT: This brief proposes an amplitude shift keying (ASK) demodulator that uses switched-capacitor differentiators to make it compliant with the very high bit rate amendment to the ISO/IEC 14443 standard for contactless smart card applications. These differentiators detect transitions in modulated ASK signals with a carrier frequency of 13.56 MHz at data rates up to 6.78 Mb/s. The demodulator has been implemented in 0.18 μm CMOS technology. The total power consumption is under 350 μW. Measured results confirm correct operation, and it is further shown that this differentiating scheme allows the modulation index to be reduced to 2.56%.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 07/2015; 62(7):1-1. DOI:10.1109/TCSII.2015.2415653
  • [Show abstract] [Hide abstract]
    ABSTRACT: The time to process each of the processing blocks of a median calculation method on a set of -bit integers is improved here by a factor of three compared with literature. The parallelism uncovered in blocks containing -bit slices is exploited by independent accumulative parallel counters so that the median is calculated faster than any known previous method for any values. The improvements to the method are discussed in the context of calculating the median for a moving set of integers, for which a pipelined architecture is developed. An extra benefit of a smaller area for the architecture is also reported.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 07/2015; 62(7):1-1. DOI:10.1109/TCSII.2015.2415655
  • [Show abstract] [Hide abstract]
    ABSTRACT: We present a low-voltage low-power CMOS subthreshold voltage reference with no resistors and no bipolar junction transistors in a wide temperature range. The temperature stability is improved by second-order compensation. By employing a bulk-driven technique and the MOS transistors working in the subthreshold region, the supply voltage and the power dissipation are reduced. Moreover, a trimming circuit is adopted to compensate for the process-related reference voltage variation. The proposed voltage reference has been fabricated with the 0.18- 1.8-V CMOS process. The measurement results show that the minimum power supply voltage is 0.45 V, the power consumption is 14.6 nW, the average temperature coefficient measured from to 125 °C is 63.6 ppm/°C, and the line regulation is 1.2 mV/V in the power supply voltage ranging from 0.45 to 1.8 V. In addition, the chip area is 0.012 mm2.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 07/2015; 62(7):1-1. DOI:10.1109/TCSII.2015.2415292
  • [Show abstract] [Hide abstract]
    ABSTRACT: As the complexity of communications and signal processing systems increases, so does the number of blocks or elements that they have. In many cases, some of those elements operate in parallel, performing the same processing on different signals. A typical example of those elements are digital filters. The increase in complexity also poses reliability challenges and creates the need for fault-tolerant implementations. A scheme based on error correction coding has been recently proposed to protect parallel filters. In that scheme, each filter is treated as a bit, and redundant filters that act as parity check bits are introduced to detect and correct errors. In this brief, the idea of applying coding techniques to protect parallel filters is addressed in a more general way. In particular, it is shown that the fact that filter inputs and outputs are not bits but numbers enables a more efficient protection. This reduces the protection overhead and makes the number of redundant filters independent of the number of parallel filters. The proposed scheme is first described and then illustrated with two case studies. Finally, both the effectiveness in protecting against errors and the cost are evaluated for a field-programmable gate array implementation.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 07/2015; 62(7):1-1. DOI:10.1109/TCSII.2015.2404219
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this brief, a low-overhead self-healing method for current matching in current-steering digital-to-analog converters (CS-DACs) is demonstrated. In contrast to traditional calibration methods that adjust current values, a statistical element selection (SES) algorithm optimizes the selection of unary current cells via combinatorial redundancy. This SES-based self-healing method relaxes the matching requirements for the current source array and achieves high static linearity at a minimum overhead cost of one current comparator and one digital controller. Moreover, this proposed low-overhead method is fully compatible with other segmented CS-DAC designs. A 14-bit CS-DAC design with on-chip self-healing control loop was implemented in 130-nm CMOS technology to demonstrate the proposed approach. The core area of the prototype chip was measured as 0.9 , with less than 0.1 occupied by the current source array. After self-healing, the INLmax was measured as 0.64 least significant bit and spurious-free dynamic range was 85 dB for a 2-MHz input signal at 200-MS/s sampling rate.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 07/2015; 62(7):1-1. DOI:10.1109/TCSII.2015.2404222
  • [Show abstract] [Hide abstract]
    ABSTRACT: This brief considers nonlinear stability analysis of ac microgrids with constant power loads (CPLs). A microgrid is a subsystem consisting of small electrical resources, local loads, and power electronic devices. It should be noted that the presence of a CPL as a sink in a microgrid results in nonlinear behavior of the microgrid. CPLs are generally connected to an ac microgrid through a controlled rectifier and/or dc–dc converters. We model an ac microgrid with local RLC load and a CPL with power converter subsystem, which results in a set of nonlinear state–space equations. Then, Popov's absolute stability theorem is utilized to analyze stability conditions for an ac microgrid in the presence of CPL. Simulation results are presented, which are in agreement with the analytical approach.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 07/2015; 62(7):1-1. DOI:10.1109/TCSII.2015.2406353
  • Circuits and Systems II: Express Briefs, IEEE Transactions on 06/2015; 62(6):1-1. DOI:10.1109/TCSII.2015.2407233
  • [Show abstract] [Hide abstract]
    ABSTRACT: This brief presents a dominating error region strategy (DERS) that improves the bit-flipping (BF) low-density parity-check decoder for solid-state drives. With the help of the DERS, the state-of-the-art BF decoding algorithms achieve better error correction performance while taking less iterations. Specifically, the DERS provides solutions for restricting the occurrences of an even number of flipped bits and bit-error propagations, both of which are intrinsic problems to current BF decoding algorithms. The DERS can be implemented with a simple circuitry and serve as a fine-tuning technique for the decoding reliability–performance tradeoff. In this brief, the DERS is evaluated with numerical analysis and computer simulations.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 06/2015; 62(6):1-1. DOI:10.1109/TCSII.2015.2407732
  • [Show abstract] [Hide abstract]
    ABSTRACT: This brief proposes a new topology for implementing differential null convention logic gates. The new topology relies on the static implementation of conventional versions of such gates and uses a set of extra minimum-sized transistors to cut off connections to the power rails in specific nodes while the gate is switching. It shows that albeit the extra transistors adding cost in area, they enable solid savings in dynamic and static power and improve transition delays. Electrical simulation results for a Kogge-Stone adder case study led to savings of 67.3% in dynamic power, 61.9% in static power, 67.2% in energy per operation, and 8.9% in forward propagation delay, when compared with a state-of-the-art differential topology.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 06/2015; 62(6):1-1. DOI:10.1109/TCSII.2015.2407198
  • [Show abstract] [Hide abstract]
    ABSTRACT: We develop a kernel adaptive filter for quaternion data based on maximizing correntropy. We apply a modified form of the HR calculus that is applicable to Hilbert spaces for evaluating the cost function gradient to develop the quaternion kernel maximum correntropy (KMC) algorithm. The KMC method uses correntropy to measure similarity between the filter output and the desired response. Here, the approach is applied to quaternions for improving performance for biased or non-Gaussian signals compared with the minimum mean square error criterion of the kernel least-mean-square algorithm. Simulation results demonstrate the improved performance with non-Gaussian inputs.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 06/2015; 62(6):1-1. DOI:10.1109/TCSII.2015.2407751