Circuits and Systems II: Express Briefs, IEEE Transactions on (IEEE T CIRCUITS-II )

Publisher: IEEE Circuits and Systems Society; Institute of Electrical and Electronics Engineers

Description

  • Impact factor
    1.33
    Show impact factor history
     
    Impact factor
  • 5-year impact
    1.52
  • Cited half-life
    6.50
  • Immediacy index
    0.21
  • Eigenfactor
    0.02
  • Article influence
    0.87
  • Other titles
    IEEE transactions on circuits and systems. II, Express briefs, Express briefs, Transactions on circuits and systems., Circuits and systems., IEEE transactions on circuits and systems
  • ISSN
    1549-7747
  • OCLC
    54412334
  • Material type
    Periodical, Internet resource
  • Document type
    Journal / Magazine / Newspaper, Internet Resource

Publications in this journal

  • [Show abstract] [Hide abstract]
    ABSTRACT: The hysteresis loop pinched at the origin of the v-i characteristic is the well-known fingerprint of the memristor excited by sinusoidal signal. This paper generalizes the present knowledge of the parameters of the pinched hysteresis loop for a periodical zero-DC driving signal described by an odd function of time. The paper concurrently brings new relationships between the parameter vs. state map characteristics, the type of the excitation, and the type of the loop pinching.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2014;
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    ABSTRACT: This brief presents a global-shutter imager readout architecture that allows a dynamic range (DR) of more than 132 dB and a high frame rate. It is based on a stacked technology where the top tier contains the back-illuminated pixel array, and the bottom tier contains the subpixel logic array, which implements the dynamic-range extension by selecting the best integration time for each pixel. Experimental results of a 64 $times$ 64 subpixel array confirm the effectiveness of the proposed method in extending the DR by more than 10 bits. The application of the algorithm to higher array resolutions compromises its effectiveness given the increased column capacitance. As a way out, we propose a novel source-follower-based buffer that reduces the settling time of the subpixel without increasing its size. The performed analysis shows that the sensor can reach 1900 and 375 fps, respectively, at full HD and at 8-K resolutions.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 04/2014;
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    ABSTRACT: A novel 1-D sampling method is proposed to calculate 2-D diamond-shaped discrete frequency distributions, which are often treated in the harmonic balance method. The proposed method fills up the entire 2-D discrete frequency plane with diamond-shaped rhombic tiles and makes the number of sampling points equal to that of the necessary frequency components.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(4):269-273.
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    ABSTRACT: This brief investigates a tradeoff between the integral squared error and the peak deviation error for a variable fractional delay (VFD) filter with a coefficient relationship. The integral squared error is minimized subject to additional constraints on the peak deviation error. The problem is solved by utilizing second-order cone programming. In addition, the performance of the VFD filter with discrete coefficients is investigated, in which the filter coefficients are expressed as the sum of power-of-two terms to reduce the filter operations to shifts and adds. Design examples show that the peak deviation error can be significantly reduced from the least squares solution while maintaining approximately the same integral squared error. Similarly, the integral squared error can be significantly reduced from the minimax solution while maintaining approximately the same peak deviation error. Furthermore, the tradeoff filters are less sensitive with respect to quantization than the least squares and minimax solutions.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(1):36-40.
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    ABSTRACT: In this brief, a 1/10-rate bang–bang phase detector (BBPD) using a single edge-tracking clock and a phase interpolator (PI)-based clock and data recovery (CDR) circuit with the proposed BBPD is presented. While a typical 1/ $N$-rate BBPD uses 2 $N$ clocks for data sampling and edge tracking, the proposed 1/ $N$ rate BBPD uses only $N + 1$ clocks, $N$ for data sampling and 1 for edge tracking. The power consumption of the CDR with the proposed 1/ $N$-rate BBPD is decreased. The reduction of the jitter tracking bandwidth of the CDR is compensated by the proposed data-encoding method. The 1/10-rate PI-based CDR with the proposed BBPD is implemented using a 0.18- $muhbox{m}$ CMOS process technology. The bit error ratio of less than $10^{-12}$ is achieved at the effective data rate of 6.93 Gb/s using encoded $2^{31} - 1$ pseudorandom binary-sequence data inputs. The power consumption of the CDR is 29.4 mW at the supply voltage of 1.8 V and the active area is 0.117 $hbox{mm}^{2}$. The effective power efficiency of the CDR is 4.24 mW/Gb/s.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(4):239-243.
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    ABSTRACT: A 10-bit 40-MS/s analog-to-digital converter (ADC) that is suitable for wireless access in vehicular environment applications is introduced. In order to satisfy the severe requirement of a wide range operating temperature under the given constraints, the ADC was simplified by eliminating nonessential building blocks such as reference drivers, a sample-and-hold amplifier (SHA), and level shifters. The proposed internal signal amplification method extends the effective signal range in both multiplying digital-to-analog converter and flash ADC, as well as the error correction range. A new clock generation circuit for a SHA-less pipelined ADC removes the need for a higher frequency external clock. The prototype ADC was fabricated in a 180-nm CMOS process. The ADC core consumes 23.4 mW at 3.3-V/1.8-V supplies. The measured worst differential nonlinearity and integral nonlinearity were $-0.52/!+0.7$ LSB and $-0.86/ !+0.9$ LSB, respectively, at a temperature of $-40 ^{circ} hbox{C}$. The signal-to-noise-and-distortion ratio stayed above 55 dB in the Nyquist condition in a temperature range of $-40 ^{circ}hbox{C}{-}125 ^{circ}hbox{C}$, which is about a 0.5 effective-number-of-bits drop from the room-temperature result.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(1):6-10.
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    ABSTRACT: In this brief, the authors propose time-quantized pseudorandom sampling (TQ-PRS) as a power-saving solution compared with conventional uniform sampling. Due to its ability to reduce replicas' power levels, TQ-PRS reduces the design constraints on receiver components. Applied on the baseband stage of a multistandard radio receiver, TQ-PRS allows decreasing the antialiasing filter order, as well as reducing the sampling frequency. This feature leads to saving up to 30% of baseband power consumption.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(6):443-447.
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    ABSTRACT: Networked predictive control (NPC) is an effective technique to compensate for transmission delays and packet dropout in networked control systems (NCS). By introducing an auxiliary error variable, in this brief, the NCS with NPC is transformed to a coupled switched system. Then, based on the switched system theory and the small gain theorem, a new stability criterion is developed under the restrictions of unstable sampling point rate. As a special case that all switched systems are Schur stable, the proposed criterion is equivalent to existing ones. The proposed stability criterion is much less conservative than existing ones, as shown from both theory and numerical simulations.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(6):453-457.
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    ABSTRACT: A new conjugate symmetric discrete orthogonal transform (CS-DOT)-generating method is proposed. The spectra of the CS-DOT for real input signals are conjugate symmetric so that we only need half memory size to store data. Meanwhile, the proposed CS-DOT also has a radix-2 fast algorithm so that it is suitable for hardware implementation. The CS-DOT generalized the existing transforms such that the discrete Fourier transform (DFT) and the conjugate symmetric sequency-ordered complex Hadamard transform (CS-SCHT) are special cases of the CS-DOT. The CS-DOT-generating method is more systematic and generalized than that of the original CS-SCHT. We can use the same implementation structure but only adjust the twiddle factors to construct the CS-SCHT and DFT so that it is easy to switch the behaviors between these transforms.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(4):284-288.
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    ABSTRACT: This brief presents a convergence analysis and simulation for a new algorithm intended for use in systems with an output power constraint. For example, in an active noise control system that generates an antinoise output to destructively cancel the noise source, we impose the additional requirement of limiting the maximum output power level to prevent system overdrive. The result is a computationally efficient algorithm that allows an explicit power level to be set.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(5):364-367.
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    ABSTRACT: Pinning control synchronization of complex networks is a fascinating and hot issue in the field of nonlinear science. However, the existing works are all based on a continuous-time feedback control strategy and assume that each network node can have continuous access to the states of its neighbors. This brief presents a novel distributed event-triggered mechanism for pinning control synchronization of complex networks. The control of nodes is only triggered at their own event time, which effectively reduces the frequency of controller updates compared with continuous-time feedback control. Considering limited communication, the new approach successfully avoids the continuous communication used for calculating the error thresholds in the event-triggered mechanism. In addition, we also develop a new alternative iterative algorithm that can further reduce the consumption of computing and communication resources to some extent. Finally, simulation results show the effectiveness of the proposed approaches and illustrate the correctness of the theoretical results.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(7):541-545.
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    ABSTRACT: This brief addresses the distributed ${cal H}_{infty}$ consensus problem of multiagent systems with higher order linear dynamics and switching directed topologies. Without assuming that the directed communication topology is fixed or balanced, a class of distributed protocols is constructed and employed to achieve state consensus while guaranteeing a prescribed disturbance rejection objective, with both admissible exogenous disturbances and unknown initial states. By using tools from algebraic graph theory and switched systems theory, it is proven that the distributed ${cal H}_{infty}$ consensus in closed-loop multiagent systems with switching directed topologies can be achieved if the feedback gain matrix of the protocol is appropriately designed and the coupling strength among neighboring agents is larger than a derived positive value. Moreover, the consensus rate for the closed-loop nominal multi-agent systems is discussed.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(5):359-363.
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    ABSTRACT: A wideband inductance–capacitance voltage-controlled oscillator (VCO) with a $g_{m}$-switching technique was designed and fabricated in the 65-nm CMOS process. With a switchable secondary gate-biased active core and a primary core, the VCO operates in two different modes. In the LF mode, in which switches turn on the secondary core, the increased start-up gain facilitates LF oscillation. In the HF mode, in which the switches isolate the secondary core from the primary core, the reduced capacitive loading allows for HF oscillation. In addition, since the gate bias of the secondary core transistors guarantees the high transconductance of the secondary core, the switch size can be minimized, which further extends the upper boundary of the oscillation frequency. The VCO achieved a 41 $%$ frequency range, i.e., 3.36–5.1 GHz, and a phase noise of $-$123.1 dBc/Hz at an offset of 1 MHz from an output frequency of 4.21 GHz. The active silicon area was 0.24 $hbox {mm}^{2}$, and the power consumption was 8.7 mW at 5 GHz.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(5):289-293.
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    ABSTRACT: This brief proposes a delta–sigma modulator that operates at extremely low voltage without using a clock boosting technique. To maintain the advantages of a discrete-time integrator in oversampled data converters, a mixed differential difference amplifier (DDA) integrator is developed that removes the input sampling switch in a switched-capacitor integrator. Conventionally, many low-voltage delta–sigma modulators have used high-voltage generating circuits to boost the clock voltage levels. A mixed DDA integrator with both a switched-resistor and a switched-capacitor technique is developed to implement a discrete-time integrator without clock boosted switches. The proposed mixed DDA integrator is demonstrated by a third-order delta–sigma modulator with a feedforward topology. The fabricated modulator shows a 68-dB signal-to-noise-plus-distortion ratio for a 20-kHz signal bandwidth with an oversampling ratio of 80. The chip consumes 140 $muhbox{W}$ of power at a true 0.4-V power supply, which is the lowest voltage without a clock boosting technique among the state-of-the-art modulators in this signal band.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(4):229-233.
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    ABSTRACT: This brief presents a fully integrated CMOS receiver that is capable of dual-mode frequency-modulated continuous-wave (FMCW) and ultrawideband (UWB) radar operations using the 0.13- $muhbox{m}$ CMOS technology. The circuit consists of a low-noise amplifier, active mixers, an in-phase and quadrature generator, and buffers. In the proposed receiver, not only the gain but also the bandwidth of the overall receiver can be tailored by the switching of the center frequencies of stages and without lowering the quality factor of each stage. As a result, the receiver achieves a conversion gain of 36.7 dB, a 1-dB power gain compression point (P1dB) of $-$29.7 dBm, and a double sideband (DSB) noise figure (NF) of 6.1 dB in the narrowband FMCW mode. The receiver also achieves a conversion gain of 27.4 dB with a 3-dB bandwidth of 6.1 GHz, a P1dB of $-$21.6 dBm, and a DSB NF of 7.4 dB in the UWB pulse mode. Its performance is comparable with that of previously published chips that only operate in a single mode.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(6):393-397.
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    ABSTRACT: This brief presents and evaluates a pre-coding algorithm to reduce power consumption and improve data retention in NAND-based solid-state drives. Compared to the state-of-the-art asymmetric coding and stripe pattern elimination algorithm, the proposed write pattern format algorithm (WPFA) achieves better data retention while consuming less power. The hardware for WPFA is simpler and requires less circuitry. The performance of WPFA is evaluated by both computer simulations and field-programmable gate array implementation.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(7):516-520.
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    ABSTRACT: In this brief, we analyze the local stochastic dynamics of a recently proposed network-based model of collective behavior in systems of self-propelled particles. In this model, each agent is assimilated to a 2-D unit vector, whose orientation changes in a discrete time setting as a result of noisy interactions with neighboring agents. The process of neighbor selection is stochastic, whereby each agent averages its orientation with a randomly chosen subset of neighbors. We linearize the model in the neighborhood of its ordered state, where all the vectors share the same orientation, and study the effect of noise on the system response. Closed-form results are validated against numerical simulations for small and large networks.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(1):44-48.
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    ABSTRACT: As process technology scales down, sensing becomes difficult during read operations because the supply voltage, i.e., $V_{DD}$, decreases and the process variation increases. Thus, a high enough sensing yield cannot be obtained with a conventional sensing circuit in deep submicron process technology. In this brief, a split-path sensing circuit is proposed to achieve a large enough sensing margin by using a variable reference voltage. The proposed sensing circuit is verified using Monte Carlo HSPICE simulation with industry-compatible low-leakage 45-nm model parameters. The proposed circuit has a sensing yield of 99% for 1-Mb memory with a sensing time of 1 ns and a sensing yield of 99% for 32-Mb memory with a sensing time of 3 ns.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(3):193-197.
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    ABSTRACT: In this brief, the logic operations involved in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)-based CSLA are analyzed to study the data dependence and to identify redundant logic operations. We have eliminated all the redundant logic operations present in the conventional CSLA and proposed a new logic formulation for CSLA. In the proposed scheme, the carry select (CS) operation is scheduled before the calculation of final-sum, which is different from the conventional approach. Bit patterns of two anticipating carry words (corresponding to $c_{rm in} = 0 hbox{and} 1$) and fixed $c_{rm in}$ bits are used for logic optimization of CS and generation units. An efficient CSLA design is obtained using optimized logic units. The proposed CSLA design involves significantly less area and delay than the recently proposed BEC-based CSLA. Due to the small carry-output delay, the proposed CSLA design is a good candidate for square-root (SQRT) CSLA. A theoretical estimate shows that the proposed SQRT-CSLA involves nearly 35% less area–delay–product (ADP) than the BEC-based SQRT-CSLA, which is best among the existing SQRT-CSLA designs, on average, for different bit-widths. The application-specified integrated circuit (ASIC) synthesis result shows that the BEC-based SQRT-CSLA design involves 48% more ADP and consumes 50% more energy than the proposed SQRT-CSLA, on average, for different bit-widths.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2014; 61(6):418-422.

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