Circuits and Systems II: Express Briefs, IEEE Transactions on Journal Impact Factor & Information

Publisher: IEEE Circuits and Systems Society; Institute of Electrical and Electronics Engineers, Institute of Electrical and Electronics Engineers

Journal description

Current impact factor: 1.19

Impact Factor Rankings

2015 Impact Factor Available summer 2015
2013 / 2014 Impact Factor 1.187
2012 Impact Factor 1.327
2011 Impact Factor 1.41
2010 Impact Factor 1.334
2009 Impact Factor 1.32
2008 Impact Factor 1.436
2007 Impact Factor 1.104

Impact factor over time

Impact factor
Year

Additional details

5-year impact 1.52
Cited half-life 6.50
Immediacy index 0.21
Eigenfactor 0.02
Article influence 0.87
Other titles IEEE transactions on circuits and systems. II, Express briefs, Express briefs, Transactions on circuits and systems., Circuits and systems., IEEE transactions on circuits and systems
ISSN 1549-7747
OCLC 54412334
Material type Periodical, Internet resource
Document type Journal / Magazine / Newspaper, Internet Resource

Publisher details

Institute of Electrical and Electronics Engineers

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  • Classification
    ​ green

Publications in this journal

  • [Show abstract] [Hide abstract]
    ABSTRACT: A digital background calibration technique for pipelined analog-to-digital converters (ADCs) is proposed to correct the capacitor mismatch, finite DC gain and nonlinearity of residue amplifiers. It divides the pipelined ADC into two equal channels and changes the decision points of sub-ADCs with a pseudo random sequence to perform the digital background calibration. The difference between the digital outputs of the channels is used to drive the least mean square (LMS) machine to correct the mentioned errors and also the mismatch between the channels. In order to speed up the error correction, an accurate estimation for the errors is identified. The estimation is done by utilizing a piecewise linear model and slope mismatch measurement technique in digital domain. Behavioral simulations of a 12-bit 100 MS/s split pipelined ADC show that the convergence time of the proposed LMS calibration technique is reduced significantly in comparison with the conventional LMS algorithm for the same signal-to-noise and distortion ratio (SNDR)
    Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2015; DOI:10.1109/TCSII.2015.2435071
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    ABSTRACT: This brief investigates the consensus problem of a linear multi-agent system (MAS) with input saturation and a directed switching proximity topology. An observer-based distributed MAS control method is developed to achieve semiglobal consensus, where only relative output measurement is available for feedback. Numerical simulation is carried out to demonstrate the effectiveness of the proposed design.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2015;
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    ABSTRACT: This brief investigates the consensus problem of a linear multi-agent system (MAS) with input saturation and a directed switching proximity topology. An observer-based distributed MAS control method is developed to achieve semiglobal consensus, where only relative output measurement is available for feedback. Numerical simulation is carried out to demonstrate the effectiveness of the proposed design.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2015; DOI:10.1109/TCSII.2015.2433399
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    ABSTRACT: This brief describes an improved binary linear-to-log (Lin2Log) conversion algorithm that has been optimized for implementation on a field-programmable gate array. The algorithm is based on a piecewise linear (PWL) approximation of the transform curve combined with a PWL approximation of a scaled version of a normalized segment error. The architecture presented achieves 23 bits of fractional precision while using just one 18K-bit block RAM (BRAM), and synthesis results indicate operating frequencies of 93 and 110 MHz when implemented on Xilinx Spartan3 and Spartan6 devices, respectively. Memory requirements are reduced by exploiting the symmetrical properties of the normalized error curve, allowing it to be more efficiently implemented using the combinatorial logic available in the reconfigurable fabric instead of using a second BRAM inefficiently. The same principles can be also adapted to applications where higher accuracy is needed.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2015; 62(5):476-480. DOI:10.1109/TCSII.2014.2386252
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    ABSTRACT: A new method is presented generating grid multiwing butterfly chaotic attractors in this brief. By designing piecewise hysteresis functions to take the place of the state variables of the Lorenz system directly, a novel grid multiwing butterfly chaotic system is constructed. The Lyapunov exponent and the bifurcation diagram are studied. Furthermore, an electronic circuit is designed to implement the system. The experimental results are in agreement with numerical simulation results, which verify the availability and feasibility of this method.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2015; 62(5):496-500. DOI:10.1109/TCSII.2014.2385274
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    ABSTRACT: This brief proposed a novel geometric structure called relative hull. By using this newly introduced concept, a novel consensus algorithm of multiagent systems was established. It has been strictly proved that such an algorithm contains a much larger convergence region with respect to the widely investigated average consensus algorithms. Furthermore, applications of this algorithm to consensus of multiagent systems with compasses and consensus on a torus demonstrated the effectiveness and generality of the proposed geometric structure.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2015; 62(5):511-515. DOI:10.1109/TCSII.2014.2386258
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    ABSTRACT: This brief presents a fast-converging hybrid successive approximation register (SAR) analog-to-digital converter (ADC) based on the radix-3 and radix-2 search approaches. The radix-3 approach achieves 1.6 bits/cycle, and the radix-2 approach mitigates the effect of comparator offset and improves the accuracy of the ADC. Incorporating clock gating of comparators and efficient switching of capacitors, the proposed hybrid ADC demonstrates promising balance between hardware complexity and speed and can achieve equivalent signal-to-noise-and-distortion-ratio (SNDR) with less capacitors compared with radix-3 SAR ADC. Behavioral simulation-based results verify operation and merit of the proposed architecture. An 11-bit 45-MS/s prototype with 5% capacitor mismatch in 180-nm CMOS was simulated in SPICE and achieves 67 dB of SNDR after calibration.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2015; 62(5):426-430. DOI:10.1109/TCSII.2014.2385214
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    ABSTRACT: A circuit architecture that models hysteretic phenomena is proposed. The model is flexible enough to reproduce both rate-independent hysteresis and thermal relaxation effects (creep), commonly observed in many real-world physical systems such as piezoelectric actuators. By suitably tuning the nonlinear characteristics of the resistive elements of the network, the well-known $log(t) $ time dependence of the creep relaxation dynamics can be accurately reproduced. An identification procedure is proposed, and two test cases are discussed.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2015; 62(5):501-505. DOI:10.1109/TCSII.2014.2385412
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    ABSTRACT: This brief presents a temperature sensor operating over a wide temperature range from 25°C to 225°C for oil well instrumentation applications. The temperature sensor is implemented with a simple time-domain architecture and a mapping function at the digital back end. The mapping function eliminates the need for a band-gap reference, whose temperature coefficient deteriorates the accuracy, particularly for high and wide temperature range of operation. The time-domain implementation results in low power consumption and chip area. With digital calibration at room temperature using a field-programmable gate array, the sensor achieves a worst case inaccuracy of +1.6 °C/−1.5 °C and consumes only 20- $mu$A current under a 4.5-V supply. The chip is fabricated with a commercial partially depleted silicon-on-insulator CMOS process and occupies a chip area of 0.41 mm2.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2015; 62(5):436-440. DOI:10.1109/TCSII.2014.2386231
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    ABSTRACT: This brief describes a CMOS current-steering digital-to-analog converter (D/A converter, DAC) with a full-swing output signal. Generally, a normal current-steering DAC cannot have a full-swing output signal because conventional DACs have an inevitable voltage drop at the output current cell. In order to improve the drawbacks, we propose a new scheme of quaternary driver and an output current cell composed of both nMOS and pMOS. First, the nMOS operates from the power supply to the half of the power supply. Second, the pMOS operates independently from the half of the power supply to the ground voltage. Then, the final output voltage is obtained through a multiplexer that is driven by a quaternary driver that selects the optimized current cell. A 6-bit 1-GS/s current-steering DAC has been fabricated with Dongbu 0.11-μm 1-poly 6-metal (1P6M) CMOS technology to verify the performance of the proposed full-swing DAC. The effective chip area is 0.46 mm2, and power consumption is about 19.1 mW. The measured results reveal that the DAC has a full-swing output signal.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2015; 62(5):441-445. DOI:10.1109/TCSII.2014.2386259
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    ABSTRACT: This brief presents a circuit to harvest energy from radio-frequency electromagnetic waves. It has a front-end transformer that simultaneously matches the harvesting circuit to a standard 50- ${Omega} $ antenna and provides voltage gain, reducing the “dead-zone” of an 18-stage rectifier. The circuit is designed and prototyped in a standard 130-nm CMOS process with an active area of $200 times 250 {mu}mbox{m}^{2} $. Experimental results show a sensitivity of −25 dBm (−22 dBm without transformer) at 1.3 GHz.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2015; 62(5):1-1. DOI:10.1109/TCSII.2014.2387514
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    ABSTRACT: Memory power consumption dominates mobile system energy budgets in scaled technologies. Fast nonvolatile memory devices (NVMs) offer a tremendous opportunity to eliminate memory leakage current during standby mode. Resistive random access memory (RRAM) in a crosspoint structure is considered to be one of the most promising emerging NVMs. However, the absence of access transistors puts significant challenges on the write/read operation. In this brief, we propose a differential 2R crosspoint structure with array segmentation and sense-before-write techniques. A 64-KB RRAM device is constructed and simulated in a 28/32-nm CMOS predictive technology model and a Verilog-A RRAM model. This design offers an opportunity to use RRAM as a cache for increasing energy efficiency in mobile computing.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2015; 62(5):461-465. DOI:10.1109/TCSII.2014.2385431
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    ABSTRACT: A low-noise transconductance amplifier (LNTA) for wideband receivers based on a $g_{m} $-boosted current mirroring topology that operates over 0.6- to 10.5-GHz is presented. $g_{m}$ boosting relaxes the $G_{m}$ and $S_{11} $ bandwidth (BW) tradeoff and the noise figure (NF) and input matching tradeoff. The active feedback synthesizes a second-order input impedance profile that further extends the $S_{11}$ BW. Despite the high $G_{m} $ obtained over large BW, high linearity is maintained through the predistortion inherent in the current mirroring topology. The LNTA is used in a 65-nm CMOS wideband channelizing iterative downconversion receiver targeting spectrum and signal analysis for cognitive radio and performs active signal splitting across two paths with a total postlayout simulated $G_{m} $ of 242 mS (170 and 72 mS in paths 1 and 2, respectively). $S_{11}$ BW and $G_{m} $ BW both exceed 10.5 GHz. Minimum LNTA NFs simulated in the two paths are 4 and 4.8 dB, respectively. Simulated wideband IIP3 and blocker P1dB are +6 and +1.5 dBm, respectively. Measurements of a direct conversion receiver in path 2 closely match simulations.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2015; 62(5):431-435. DOI:10.1109/TCSII.2014.2385371
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    ABSTRACT: In this brief, we propose high-throughput digit-level systolic structure for area-delay-efficient implementation of multiplier over $mbox{GF}(2^{m} ) $ based on irreducible trinomials. We have proposed a digit-level multiplication algorithm, which allows us to compute a set of $d$ (where $d$ is the digit size) partial products in parallel in each processing element (PE) during each cycle and accumulate them across the systolic pipeline in reduced form. To enhance the throughput rate of the proposed structure, we feed the reduced operands and accumulated partial products to the PEs by independent systolic channels that reduces the critical path to $(T_{!A}+T_{X}+T_{!R})$, where $T_{!A}$, $T_{X}$, and $T_{!R}$ refer to the propagation delays of AND gate, xor gate, and bit register, respectively. From synthesis results, it is found that the proposed multiplier involves significantly lower area–time complexity and higher throughput than the existing competing designs.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2015; 62(5):481-485. DOI:10.1109/TCSII.2014.2386260
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    ABSTRACT: In this paper, a new convergence analysis is presented for a well-known sparse adaptive filter family, namely, the proportionate-type normalized least mean square (PtNLMS) algorithms, where, unlike all the existing approaches, no assumption of whiteness is made on the input. The analysis relies on a “transform” domain based model of the PtNLMS algorithms and brings out certain new convergence features not reported earlier. In particular, it establishes the universality of the steady-state excess mean square error formula derived earlier under white input assumption. In addition, it brings out a new relation between the mean square deviation of each tap weight and the corresponding gain factor used in the PtNLMS algorithm.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2015; 62(5):491-495. DOI:10.1109/TCSII.2014.2386261
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    ABSTRACT: Error detection and correction (EDAC) has become more important with continued device scaling. We propose a field-programmable gate array (FPGA)-based simulator to accelerate the transient simulation of pipeline-level EDAC circuits and their interactions with circuits under test (CUTs). The simulator incorporates the CUT delay profile, the CUT error profile, and the EDAC model. The FPGA-based simulator captures the fine-grained interactions between the CUT and EDAC for the evaluation of the effectiveness of EDAC and its tuning. The simulator is constructed based on parameterized models, making it general purpose and widely applicable. We demonstrate the capability of this simulator in the evaluation of two popular pipeline-level EDAC designs, i.e., preedge EDAC and postedge EDAC, using synthesized processors that operate under generic error and noise models. The proposed error simulator uncovers key insights to help guide EDAC designs.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2015; 62(5):471-475. DOI:10.1109/TCSII.2014.2386251
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    ABSTRACT: Table-lookup-and-addition methods provide multiplierless function evaluation using multiple lookup tables and a multioperand adder. In spite of their high-speed operation, they are only practical in low-precision applications due to the fast increase in table size with precision width. In this brief, we present two methods for table size reduction by decomposing the original table of initial values into two or three tables with fewer entries and/or smaller bit width. The proposed table decompositions do not incur any extra rounding errors so that the original table can be completely recovered. Experimental results demonstrate significant saving of table sizes compared with the best of the prior designs of the multipartite methods.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2015; 62(5):466-470. DOI:10.1109/TCSII.2014.2386232
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    ABSTRACT: This brief presents a low-power CMOS image sensor with 14-bit column-parallel two-step (TS) successive approximation (SA) analog-to-digital converters (ADCs). The proposed TS SA ADC adopts a pseudomultiple sampling method to reduce the power consumption and the area. For implementing the 14-bit ADC, it only uses a capacitor digital-to-analog converter of 6 bits rather than 14 bits. The multiple sampling also suppresses the noise of a pixel and a column-parallel ADC. The image sensor is fabricated by using the 0.13-μm CMOS process. The measurement results show that the temporal noise is 82.7 μVrms, and the power consumption is 55.1 μW for one column ADC with a programmable gain amplifier. With the digital correlated double sampling and the TS calibration method, the proposed ADC achieves the column fixed-pattern noise of 0.98 LSB and a differential nonlinearity of +0.99/−0.90 LSB.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2015; 62(5):1-1. DOI:10.1109/TCSII.2014.2387531
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    ABSTRACT: This brief derives efficient two-stage-based polyphase structures for arbitrary-integer sampling rate conversion. For even-integer conversions, the overall structures correspond to parallelized conventional two-stage structures, but the derivations in this brief offer further insights when comparing the two cases of odd- and even-integer conversions. For the class of linear-phase finite-length impulse response $M$th-band filters, it is then demonstrated through design examples that conversions by odd factors are in fact more efficient than by even factors.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2015; 62(5):1-1. DOI:10.1109/TCSII.2015.2389291