Journal of Electronic Packaging, Transactions of the ASME

Publisher: American Society of Mechanical Engineers

Journal description

Current impact factor: 0.86

Impact Factor Rankings

2015 Impact Factor Available summer 2016
2014 Impact Factor 0.856
2013 Impact Factor 0.645
2012 Impact Factor 0.934
2011 Impact Factor 0.694
2010 Impact Factor 0.564
2009 Impact Factor 0.781
2008 Impact Factor 0.827
2007 Impact Factor 0.583
2006 Impact Factor 0.487
2005 Impact Factor 0.428
2004 Impact Factor 0.383
2003 Impact Factor 0.378
2002 Impact Factor 0.33
2001 Impact Factor 0.47
2000 Impact Factor 0.359
1999 Impact Factor 0.31
1998 Impact Factor 0.345
1997 Impact Factor 0.12

Impact factor over time

Impact factor

Additional details

5-year impact 0.84
Cited half-life 8.70
Immediacy index 0.12
Eigenfactor 0.00
Article influence 0.24
ISSN 1528-9044

Publisher details

American Society of Mechanical Engineers

  • Pre-print
    • Author cannot archive a pre-print version
  • Post-print
    • Author cannot archive a post-print version
  • Classification
    ​ white

Publications in this journal

  • [Show abstract] [Hide abstract]
    ABSTRACT: The local surface temperature, heat flux, heat transfer coefficient, and Nusselt number were measured for an inline array of circular, normal jets of single-phase, liquid water impinging on a copper block with a common outlet for spent flow, and an experimental two-dimensional (2D) surface map was obtained by translating the jet array relative to the sensors. The effects of variation in jet height, jet pitch, confining wall angle, and average jet Reynolds number were investigated. A strong interaction between the effects of the geometric parameters was observed, and a 5 deg confining wall was seen to be an effective method of managing the spent flow for jet impingement cooling of power electronics. The maximum average heat transfer coefficient of 13,100 W/m2 K and average Nusselt number of 67.7 were measured at an average jet Reynolds number of 14,000.
    Journal of Electronic Packaging, Transactions of the ASME 09/2015; 137(3). DOI:10.1115/1.4030953
  • [Show abstract] [Hide abstract]
    ABSTRACT: FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow process. In this paper, WLPs with FeNi and Cu UBM were fabricated and their board level reliabilities were studied comparatively. The WLP samples assembled on the printed circuit board (PCB) were subjected to temperature cycling and drop tests according to JEDEC standards. The results showed that the reliability of WLP with FeNi UBM was a little lower than that with Cu UBM. The main failure modes for both FeNi and Cu UBM samples in temperature cycling test were the crack in IMC or solder ball on PCB side. And detachments between UBM and the redistribution layer (RDL) were also observed in Cu UBM WLPs. In drop test, the crack of RDL was found in all failed FeNi UBM samples and part of Cu UBM ones, and the primary failure mode in Cu UBM samples was the crack of IMC on PCB side. In addition, the finite element analysis (FEA) was carried out to further understand the difference of the failure modes between the FeNi UBM samples and the Cu UBM samples. The high stress was observed around the UBM and the pad on PCB in the temperature cycling model. And the maximum stress appeared on the RDL in the drop simulation, which was obviously larger than that on the pad. The FEA results showed that the introduction of FeNi UBM increased the stress levels both in temperature cycling and drop tests. Thus, the FeNi alloy cannot simply replace Cu as UBM in WLP without further package structural optimization.
    Journal of Electronic Packaging, Transactions of the ASME 09/2015; 137(3). DOI:10.1115/1.4030974
  • [Show abstract] [Hide abstract]
    ABSTRACT: In situ sensors can measure wire bond reliability nondestructively during thermal aging. Conventional thermal aging of ball bonds requires ovens heating the entire microchip along with the wire bonds, also affecting interconnects for in situ sensors. To protect the interconnects and on-chip logic components of in situ sensor chips, conventional thermal aging is kept below a safe temperature limit of 200°C. At higher temperatures, the doped Si components change their characteristics and transistors stop working. Localized on-chip heating is introduced to circumvent these drawbacks using a new microheater to increase the safe temperature limit for nondestructive reliability assessment with in situ sensors. The effect of temperature on surrounding components is reduced. The microheater is a rectangular design resistive heater made from N+ silicon. In addition, a pad resistance measurement is introduced that indicates bond aging more conveniently than previously reported bond resistance measurements.
    Journal of Electronic Packaging, Transactions of the ASME 03/2015; 137(1). DOI:10.1115/1.4028281
  • [Show abstract] [Hide abstract]
    ABSTRACT: Computer servers can be represented by lumped thermal capacitances for the purpose of simulating server and data center transient thermal response to changes in operating conditions or equipment failures. Two parameters are needed to characterize the transient behavior of a lumped-capacitance server: its thermal capacitance and its thermal conductance, heat transfer effectiveness, or time constant. To avoid the laborious task of obtaining these parameters from measurements or estimations of the thermal characteristics of internal components of the server, a method is proposed to derive these parameters from external measurements that can be easily obtained without performing an “autopsy” on the server. In this paper, we present the mathematical formulation underlying the proposed method and describe how the parameters are to be obtained from external air-temperature measurements using the mathematical model. We then present validation test cases using experimental data from server shut-down and inlet-temperature ramp tests. The experimentally obtained parameters are implemented into a computational fluid dynamics (CFD) case study of server shutdown in which the transient server exit air temperature is computed from the lumped-capacitance parameters via a user-defined function. The results thus obtained are in excellent agreement with the experimental data.
    Journal of Electronic Packaging, Transactions of the ASME 05/2014; 136(3):031005. DOI:10.1115/1.4027092
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    ABSTRACT: This study goes beyond the common micro-channel cooling system composed of uniform parallel straight micro-channels. Due to the highly non-uniform power dissipation on a multicore processor, the micro-channel cooling system is designed to fit with the heat load on the multicore processor. By applying effective strategies and arranging key design parameters, stronger cooling is provided under the high power core area, and less cooling is provided under the low power cache area to save the precious pumping power. The well designed thermal-aware micro-channel cooling systems could effectively lower the hot spot temperature and temperature gradients on chip.A three-stage approach to design thermal-aware micro-channel cooling system for multicore processor is developed. Two micro-channel cooling systems are specifically designed for a 2 core 150W Intel Tulsa processor and an 8 core 260W (doubled power) Intel Nehalem processor, to illustrate the design approach. The working fluid is single phase HFE7100. For the Tulsa processor, a strategy named strip-and-zone approach is used. The final design leads to 30kPa pressure drop and 0.094W pumping power while maintains the hot spot temperature to be 75 °C. For the Nehalem processor, a split flow micro-channel system and a widen-inlet strategy are applied. The final design takes 15kPa pressure drop and 0.0845W pumping power while maintains the hot spot temperature to be 82.8 °C. The design approach in this study provides the basic guide for the industrial applications of effective multicore processor cooling using micro-channels.
    ASME 2013 International Mechanical Engineering Congress and Exposition; 11/2013
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    ABSTRACT: The development of a solder-based vacuum bonding technique for micro-electro mechanical systems (MEMS) applications is presented. A chip with a micro-sensor was bonded to a cover plate to form a sealed cavity. The method relies on a solder-based hybridization comprising a self-assembly process that takes advantage of the surface tension and viscous forces of the solder. A model of the assembly was developed to predict the capillary instability of the solde, and the dynamic behavior of the assembled chip. Experimental results showed that a molten bead with parallel contact lines is stable when the ratio between the solder height and solder width is less than one half. Misalignment attributed to the self-assembly process was within a few microns. Fractographic analysis and leak and shear tests confirmed the predicted sealing and mechanical characteristics of the bonding. This method is especially suitable for bonding wafers in a vacuum for MEMS and other micro-devices, at low manufacturing temperatures (∼250 °C).
    Journal of Electronic Packaging, Transactions of the ASME 01/2012; 134(1):011009. DOI:10.1115/1.4006138