IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Publications in this journal
Conference Proceeding: Selective instruction set muting for energy-aware adaptive processors[show abstract] [hide abstract]
ABSTRACT: We propose a new way to save energy in adaptive processors. According to an execution context the custom instruction set of an adaptive processor is selectively 'muted' at run time and thus the energy efficiency is significantly increased. Implemented are multiple so-called 'muting modes' each leading to particular leakage energy savings. A key challenge of this work is to determine which of the muting modes are beneficial for which part of the custom instruction set in a specific execution context. We demonstrate the feasibility by means of an H.264 video encoder (although not limited to that) for various technology nodes. The complex and unpredictable processing behavior of an H.264 encoder represents thereby a real-world scenario. Our results show on average more than 30% energy savings compared to state-of-the-art. We claim that adaptive processors (and reconfigurable computing in general) would be far more energy efficient if FPGA vendors would provide a basic infrastructure that is necessary to exert our novel technique.IEEE/ACM International Conference on Computer-Aided Design (ICCAD); 02/2013
Conference Proceeding: Reactant minimization during sample preparation on digital microfluidic biochips using skewed mixing treesComputer-Aided Design (ICCAD), 2012 IEEE/ACM International Conference on; 01/2012
Conference Proceeding: Scalable segmentation-based malicious circuitry detection and diagnosis[show abstract] [hide abstract]
ABSTRACT: Hardware Trojans (HTs) pose a significant threat to the modern and pending integrated circuit (IC). Several approaches have been proposed to detect HTs, but they are either incapable of detecting HTs under the presence of process variation (PV) or unable to handle very large circuits in the modern IC industry. We develop a scalable HT detection and diagnosis scheme by using segmentation techniques and gate level characterization (GLC). In order to address the scalability issue, we propose a segmentation method which divides the large circuit into small sub-circuits by using input vector control. We propose a segment selection model in terms of properties of segments and their effects on GLC accuracy. The model parameters are calibrated by sampled data from the GLC process. Based on the selected segments we are able to detect and diagnose HTs correctly by tracing gate level leakage power. We evaluate our approach on several ISCAS85/ISCAS89/ITC99 benchmarks. The simulation results show that our approach is capable of detecting and diagnosing HTs accurately on large circuits.Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on; 12/2010
Conference Proceeding: A robust functional ECO engine by SAT proof minimization and interpolation techniques[show abstract] [hide abstract]
ABSTRACT: Functional rectification in late design stages has been a crucial process in modern complex system design. This paper proposes a robust functional ECO engine, which applies SAT proof minimization and interpolation techniques to automate patch construction to make old implementation and golden specification functionally equivalent. The SAT proof minimization technique provides a sound and efficient way of fixing easy errors, and the interpolation technique provides a complete and robust way of fixing remaining errors. Experimental results show that our engine performs robustly to generate small patches in fixing various design rectification instances.Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on; 12/2010
Conference Proceeding: Maximum-information storage system: Concept, implementation and application[show abstract] [hide abstract]
ABSTRACT: The aggressive technology scaling has made it increasingly difficult to design high-performance, high-density SRAM circuits. In this paper, we propose a new SRAM design methodology that is referred to as maximum-information storage system (MISS). Unlike most traditional SRAM circuits that are designed for maximum cell density, MISS aims to maximize the information density (i.e., the number of information bits per unit area). Towards this goal, an information model is derived to quantitatively measure the information bits stored in a given SRAM system. In addition, a convex optimization framework is developed to optimize SRAM cells to achieve maximum information storage. Our design example in a commercial 65nm CMOS process demonstrates that MISS achieves more than 3.5× area reduction over the traditional SRAM design, while storing the same amount of information. Furthermore, two real-life signal processing examples show that given the same area constraint, MISS can increase signal-to-noise ratio by more than 30 dB compared to the traditional SRAM system.Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on; 12/2010
Conference Proceeding: Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs[show abstract] [hide abstract]
ABSTRACT: Power gating has been widely adopted in multicore designs. The design of fast and reliable power mode transition for per-core power gating remains a challenging problem. This paper studies the design methodology for fast power gating wake-up with guaranteed power integrity. Two novel techniques, namely current shaping and multi-thread activation are proposed. Models and physical implementation of both techniques are analyzed. Experimental results demonstrated 1.5 to 11 times wake-up time speedup with no penalty on area or power consumptions by using the proposed techniques.Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on; 12/2010
Conference Proceeding: ESL solutions for low power design[show abstract] [hide abstract]
ABSTRACT: Power consumption has become one of the major concerns in today's integrated circuit design, and especially in System-on-Chip development where numerous heterogeneous functions are integrated in a single chip. In this context system architects have the challenge to identify power issues very early in the design flow from a complex set of use scenarios. This paper explains how to achieve this challenge through the deployment of a modeling framework that enables low power technique exploration. The principle that sustains the framework is first introduced. A description of some of the power saving techniques that can be supported together with a presentation of the modeling data then follows. A few examples finally show the results a system designer can expect using the framework.Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on; 12/2010
Conference Proceeding: Post-placement power optimization with multi-bit flip-flops[show abstract] [hide abstract]
ABSTRACT: Optimization for power is always one of the most important design objectives in modern nanometer IC design. Recent studies have shown the effectiveness of applying multi-bit flip-flops to save the power consumption of the clock network. However, all the previous works applied multi-bit flip-flops at earlier design stages, which could be very difficult to carry out the trade-off among power, timing, and other design objectives. This paper presents a novel power optimization method by incrementally applying more multi-bit flip-flops at the post-placement stage to gain more clock power saving while considering the placement density and timing slack constraints, and simultaneously minimizing interconnecting wirelength. Experimental results based on the industry benchmark circuits show that our approach is very effective and efficient, which can be seamlessly integrated in modern design flow.Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on; 12/2010
Conference Proceeding: PEDS: Passivity enforcement for descriptor systems via Hamiltonian-symplectic matrix pencil perturbation[show abstract] [hide abstract]
ABSTRACT: Passivity is a crucial property of macromodels to guarantee stable global (interconnected) simulation. However, weakly nonpassive models may be generated for passive circuits and systems in various contexts, such as data fitting, model order reduction (MOR) and electromagnetic (EM) macromodeling. Therefore, a post-processing passivity enforcement algorithm is desired. Most existing algorithms are designed to handle pole-residue models. The few algorithms for state space models only handle regular systems (RSs) with a nonsingular D+D<sup>T</sup> term. To the authors' best knowledge, no algorithm has been proposed to enforce passivity for more general descriptor systems (DSs) and state space models with singular D+D<sup>T</sup> terms. In this paper, a new post-processing passivity enforcement algorithm based on perturbation of Hamiltonian-symplectic matrix pencil, PEDS, is proposed. PEDS, for the first time, can enforce passivity for DSs. It can also handle all kinds of state space models (both RSs and DSs) with singular D+D<sup>T</sup> terms. Moreover, a criterion to control the error of perturbation is devised, with which the optimal passive models with the best accuracy can be obtained. Numerical examples then verify that PEDS is efficient, robust and relatively cheap for passivity enforcement of DSs with mild passivity violations.Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on; 12/2010
Conference Proceeding: WISDOM: Wire spreading enhanced decomposition of masks in Double Patterning Lithography[show abstract] [hide abstract]
ABSTRACT: In Double Patterning Lithography (DPL), conflict and stitch minimization are two main challenges. Post-routing mask decomposition algorithms may not be enough to achieve high quality solution for DPL-unfriendly designs, due to complex metal patterns. In this paper, we propose an efficient framework of WISDOM to perform wire spreading and mask assignment simultaneously for enhanced decomposability. A set of Wire Spreading Candidates (WSC) are identified to eliminate coloring constraints or create additional splitting locations. Based on these candidates, an Integer Linear Programming (ILP) formulation is proposed to simultaneously minimize the number of conflicts and stitches, while introducing as less layout perturbation as possible. To improve scalability, we further propose three acceleration techniques without loss of solution quality: odd-cycle union optimization, coloring-independent group computing, and suboptimal solution pruning. The experimental results show that, compared to a post-routing mask decomposition method, we are able to reduce the number of conflicts and stitches by 41% and 23% respectively, with only 0.43% wire length increase. Moreover, with proposed acceleration methods, we achieve 9× speed-up.Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on; 12/2010
Conference Proceeding: Memory access aware on-line voltage control for performance and energy optimization[show abstract] [hide abstract]
ABSTRACT: This paper describes an off-chip memory access-aware runtime DVFS control technique that minimizes energy consumption subject to constraints on application execution times. We consider application phases and the implications of changing cache miss rates on the ideal power control state. We first propose a two-stage DVFS algorithm based on formulating the throughput-constrained energy minimization problem as a multiple-choice knapsack problem (MCKP). This algorithm uses a power model that adapts to application phase changes by observing processor hardware performance counter values. The solutions it produces provide upper bounds on the energy savings achievable under a performance constraint. However, this algorithm assumes a priori (oracle or profiling-based) knowledge of application phase change behavior. To relax this assumption, we propose P-DVFS, an predictive DVFS algorithm for on-line minimization of energy consumption under a performance constraint without requiring a priori knowledge of an application's behavior. P-DVFS uses hardware performance counter based performance and power models. It predicts remaining execution time online in order to control voltage and frequency settings to optimize energy consumption and performance. The P-DVFS problem is formulated as a multiple-choice knapsack problem, which can be efficiently and optimally solved online. We evaluated P-DVFS using direct measurement of a real DVFS-equipped system. When bounding performance loss to at most 20% of that at the maximum frequency and voltage, P-DVFS leads to energy consumptions within 1.83% of the optimal solution for our problem instances on average with a maximum deviation of 4.83%. In addition to producing results approaching those of an oracle formulation, P-DVFS reduces power consumption for our problem instances by 9.93% on average, and up to 25.64%, compared with the most advanced related work.Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on; 12/2010
Conference Proceeding: Efficient state space exploration: Interleaving stateless and state-based model checking[show abstract] [hide abstract]
ABSTRACT: State-based model checking methods comprise computing and storing reachable states, while stateless model checking methods directly reason about reachable paths using decision procedures, thereby avoiding computing and storing the reachable states. Typically, state-based methods involve memory-intensive operations, while stateless methods involve time-intensive operations. We propose a divide-and-conquer strategy to combine the complementary strengths of these methods for efficient verification of embedded software. Specifically, our model checking engine uses both state decomposition and state prioritization to guide the combination of a Presburger arithmetic based symbolic traversal algorithm (state-based) and an SMT based bounded model checking algorithm (stateless). These two underlying algorithms are interleaved-based on memory/time bounds and dynamic task partitioning-in order to systematically explore the state space and to avoid storing the entire reachable state set. We have implemented our new method in a tightly integrated verification tool called HMC (Hybrid Model Checker). We demonstrate the efficacy of the proposed method on some industry examples.Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on; 12/2010
Conference Proceeding: Design space exploration and performance evaluation at Electronic System Level for NoC-based MPSoC[show abstract] [hide abstract]
ABSTRACT: System-on-Chip (SoC) has become a common design technique in the integrated circuits industry as it offers many advantages in terms of cost and performance efficiency. SoCs are increasingly complex and heterogeneous systems that are highly integrated comprising processors, caches, hardware accelerators, memories, peripherals and interconnects. Modern SoCs deploy not only simple buses but also crossbars and Networks-on-Chip (NoC) to connect dozens or even hundreds of modules. However, it is difficult to evaluate the performance of these interconnects because of their complexity. This is a potential design risk. In order to address this challenge, early design space exploration is required to find appropriate system architectures out of many candidate architectures. An appropriate interconnect architecture is a fundamental outcome of these evaluations since its latency and throughput characteristics affect the performance of all attached modules in the SoC. In this paper we show how to perform early design space exploration using our Electronic System Level (ESL) performance evaluation framework SystemQ. We use a heterogeneous MultiProcessor SoC that features a complex NoC as a central interconnect. Based on this example we show the importance of proper abstraction in order to keep simulation efforts manageable.Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on; 12/2010
Conference Proceeding: Obstacle-avoiding rectilinear Steiner minimum tree construction: An optimal approach[show abstract] [hide abstract]
ABSTRACT: In this paper, we present an efficient method to solve the obstacle-avoiding rectilinear Steiner minimum tree (OARSMT) problem optimally. Our work is a major improvement over the work proposed in. First, a new kind of full Steiner trees (FSTs) called obstacle-avoiding full Steiner trees (OAFSTs) is proposed. We show that for any OARSMT problem there exists an optimal tree composed of OAFSTs only. We then extend the proofs on the possible topologies of FSTs in to find the possible topologies of OAFSTs, showing that OAFSTs can be constructed easily. A two-phase algorithm for the construction of OARSMTs is then developed. In the first phase, a sufficient number of OAFSTs are generated. In the second phase, the OAFSTs are used to construct an OARSMT. Experimental results on several benchmarks show that the proposed method achieves 185 times speedup on average and is able to solve more benchmarks than the approach in.Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on; 12/2010
Conference Proceeding: Template-mask design methodology for double patterning technology[show abstract] [hide abstract]
ABSTRACT: Double patterning technology (DPT) has recently gained much attention and is viewed as the most promising solution for the sub-32-nm node process. DPT decomposes a layout into two masks and applies double exposure patterning to increase the pitch size and thus printability. This paper proposes the first mask-sharing methodology for DPT, which can share masks among different designs, to reduce the number of costly masks for double patterning. The design methodology consists of two tasks: template-mask design and template-mask-aware routing. A graph matching-based algorithm is developed to design a flexible template mask that tries to accommodate as many design patterns as possible. We also present a template-mask-aware routing (TMR) algorithm, focusing on DPT-related issues to generate routing solutions that satisfy the constraints induced from double patterning and template masks. Experimental results show that our designed template mask is mask-saving, and our TMR can achieve conflict-free routing with 100% routability and save at least two masks for each circuit with reasonable wirelength and runtime overheads.Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on; 12/2010
Conference Proceeding: HW/SW co-design of parallel systems[show abstract] [hide abstract]
ABSTRACT: Multicore architectures have become ubiquitous in the recent years. Yet, traditional serial programming techniques cannot exploit their potential because they do not express the dependencies of the tasks clearly rendering them unsuitable for any system which can execute tasks in parallel. We present a methodology which enables designers to explicitly and separately express function, communication and platform aspects. The approach allows to explore all aspects of a system without even building virtual prototypes or platform-dependent code. A bottleneck analysis and resolution leads to a well matched hardware/software partitioning as a basis for subsequent HW and SW design.Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on; 12/2010
Conference Proceeding: On timing-independent false path identification[show abstract] [hide abstract]
ABSTRACT: This paper is concerned with finding timing-independent false paths that cannot be sensitized under any signal arrival time condition in integrated circuits. Existing techniques regard a path as a true path as long as a vector pair can be found to sensitize it. This is rather pessimistic since such a path might be activated only with illegal states in the circuit and hence it is actually functionally-unsensitizable. In this paper, we develop novel techniques to take the above issue into consideration when identifying false paths, which facilitates us to find much more false paths than conventional techniques. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed methodology.Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on; 12/2010
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