IEEE International Test Conference (TC)

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  • ISSN
    1089-3539

Publications in this journal

  • [show abstract] [hide abstract]
    ABSTRACT: Through-silicon vias (TSVs) are crucial elements of 3-D bonded integrated circuits. Since they connect different layers of 3-D stacks, their proper operation is an essential prerequisite for the system function. This paper describes a procedure for deriving fault diagnosis test sequences to identify single and multiple defective TSVs. Additional experimental results obtained for pseudorandom patterns illustrate feasibility and robustness of the proposed test schemes in terms of their detection and diagnostic capabilities and are reported herein.
    IEEE International Test Conference (TC) 09/2013;
  • [show abstract] [hide abstract]
    ABSTRACT: Through-silicon vias (TSVs) are crucial elements of 3-D bonded integrated circuits. Since they connect different layers of 3-D stacks, their proper operation is an essential prerequisite for the system function. This paper describes a procedure for deriving fault diagnosis test sequences to identify single and multiple defective TSVs. Additional experimental results obtained for pseudorandom patterns illustrate feasibility and robustness of the proposed test schemes in terms of their detection and diagnostic capabilities and are reported herein.
    IEEE International Test Conference (TC) 09/2013;
  • [show abstract] [hide abstract]
    ABSTRACT: New methods are proposed to guide line justification and fault propagation in test generation procedures to derive compact test sets. Experiments on several industrial designs yielded, on average, 24% reduction in test set sizes.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: In this paper we present a self-test method for RF transceivers to determine IQ imbalance, time skews, IIP3, IIP5, AM/AM, and AM/PM distortion with no hardware overhead. The analysis is done through the loop-back set-up over two frames, each of which is 200us in duration. The overall measurement time is less than 10ms including the computation time. The determined parameters can be used for digital calibration, which greatly enhances reliability and yield by widening the tolerance of the parameters. We show through hardware measurements that the target performance parameters can be determined accurately and the EVM can be reduced more than 5 folds, making even highly impaired systems usable. The only additional component to enable our approach is an attenuator in the loop-back path, which can be placed outside the chip. Hence, we call this self test and calibration approach a zero overhead approach.
    Test Conference (ITC), 2013 IEEE International; 01/2013
  • [show abstract] [hide abstract]
    ABSTRACT: Wide I/O poses serious challenges due to the requisite high density of electronics and relays near the DUT, as well as high bandwidth. A 2×2mm MEMS switch has been demonstrated, offering >80% footprint reduction relative to a typical TO-can electromagnetic relay. A further benefit of its small size, the MEMS relay is able to operate up to Ka-band (40 GHz) with hot switch capability and repeatability of
    Test Conference (ITC), 2013 IEEE International; 01/2013
  • [show abstract] [hide abstract]
    ABSTRACT: Fault diagnosis of Integrated Circuits (ICs) has grown into a special field of interest in the Semiconductor Industry. Fault diagnosis is very useful at the design stage for debugging purposes, at high-volume manufacturing for obtaining feedback about the underlying fault mechanisms and improving the design and layout in future IC generations, and in cases where the IC is part of a larger safety-critical system (e.g. automotive, aerospace) for identifying the root-cause of failure and for applying corrective actions that will prevent failure reoccurrence and, thereby, will expand the safety features. In this summary paper, we present a methodology for fault modeling and fault diagnosis of analog circuits based on machine learning. A defect filter is used to recognize the type of fault (parametric or catastrophic), inverse regression functions are used to locate and predict the values of parametric faults, and multi-class classifiers are used to list catastrophic faults according to their likelihood of occurrence. The methodology is demonstrated on both simulation and high-volume manufacturing data showing excellent overall diagnosis rate.
    Test Conference (ITC), 2013 IEEE International; 01/2013
  • [show abstract] [hide abstract]
    ABSTRACT: Recently, there is an increasing need for methods of functionally testing RF devices to provide lower cost alternatives to testing RF communication systems. In this paper, a real-time functional testing method of RF-ICs using a digital tester is proposed as an alternative to conventional RF testing. The method is based on a concept of direct modulation. By employing the proposed method, the QPSK and 16-QAM signals can be generated with digital tester drivers. The method can directly compare the baseband data with its expected data through digital tester comparators without demodulation. Therefore, the proposed method does not require any modulator or demodulator. Moreover, the method can perform both a stress test of RF receivers by injecting modulation error and a margin test of RF transmitters by using a dual-threshold comparator.
    Test Conference (ITC), 2013 IEEE International; 01/2013
  • [show abstract] [hide abstract]
    ABSTRACT: In this paper, we will present two different applications of “test pattern sampling” for logic testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The drivers and implementations for these two methods were completely different - one relying on real-time analysis/optimization applied at wafer test; the other based on off-line analysis with daily updates and real-time adjustments at Final Test.
    Test Conference (ITC), 2013 IEEE International; 01/2013
  • [show abstract] [hide abstract]
    ABSTRACT: Due to the current hardware and testing environment limitations, sometimes a perfect coherent condition cannot be satisfied regarding Digital-to-Analog Converter testing. In this paper, the existing algorithms for non-coherent sampling are reviewed and the limitations of each algorithm are analyzed. Then an enhanced procedure is proposed with detail explanation. The experimental results show the new procedure has a higher accuracy and a broader coverage.
    Test Conference (ITC), 2013 IEEE International; 01/2013
  • [show abstract] [hide abstract]
    ABSTRACT: Without appropriate stitching of scan chains, even with good diagnosis algorithm and diagnostic pattern generation, it may still result in bad scan chain diagnostic resolution. To improve the diagnostic resolution, we propose a novel Diagnosis and Layout Aware (DLA) scan chain stitching method, which is pattern independent and supports embedded scan compaction. It is based on three ideas: (1) increasing the number of sensitive scan cells, which can capture useful diagnostic information; (2) properly distributing the sensitive scan cells along the scan chains to enhance the overall resolution; (3) stitching scan cells based on their placement at layout to preserve the chip performance. Experiments on ISCAS'89/ITC'99 benchmark circuits and a real industry circuit based on 20nm technology with silicon results show that, the proposed DLA scan chain stitching method effectively improves the resolution, with negligible impact on chip performance, embedded scan compaction, transition fault coverage, and test power dissipation. The silicon results even show 7X average resolution improvement comparing to without using the proposed method.
    Test Conference (ITC), 2013 IEEE International; 01/2013
  • [show abstract] [hide abstract]
    ABSTRACT: The paper describes clock gating structures in practice that can impact the testability and cause silicon failure due to the race condition or timing uncertainty such as voltage droop and the process variations. The design rule check (DRC) algorithm is presented to efficiently and robustly identify such problematic structures. Furthermore, the automatic test pattern generation (ATPG) method is proposed to handle the design with such rule violations to prevent simulation mismatches while minimizing the test coverage lost.
    Test Conference (ITC), 2013 IEEE International; 01/2013
  • [show abstract] [hide abstract]
    ABSTRACT: A conventional wafer sort test on an automatic test equipment (ATE) uses a fixed synchronous clock period. Typical test cycles may produce high signal activity and to keep the power dissipation under control, a relatively slow test clock is used. This results in long test times, especially for large scan based circuits. Observing that each test clock cycle may consume different amount of power, we propose an asynchronous clock test methodology to reduce the test time. Smallest customized clock periods for test cycles or sets of cycles are computed based on power and critical path constraints. A theoretical analysis shows that the total energy consumed by the entire test is invariant and the test time depends on the rate it is dissipated during test. An asynchronous clock test dissipates this energy at the maximum allowable rate, while the conventional synchronous clock test dissipates it at a lower average rate. The asynchronous clock test method is first implemented in simulation using several ISCAS'89 benchmark circuits. These results show test time reductions up to 47%. To establish the test programming feasibility of the new methodology the Advantest T2000GS ATE at Auburn University Test Lab was used. Test time reduction of 38% is demonstrated for scan test of a circuit. The paper ends with an investigation showing that for a circuit under test, given its power budget and a test there exists a supply voltage that minimizes the test time. An analysis determines whether the shortest test must use a synchronous or an asynchronous clock.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: The requirements for the recent mobile devices are significantly different from those for the conventional PC-oriented devices in many aspects: power consumption, performance and production ramp-up speed. These unique requirements have created many challenges in process technology, design, and manufacturing. Mobile devices are battery-sensitive, but still need the horsepower to run performance-hungry applications. We need a very tight DTCO (Design and Technology Co-Optimization), and a steep production ramp with high yield. Samsung Electronics has been focusing on the development and manufacturing of mobile devices for many years. The unique challenges associated with mobile devices will be addressed in the talk, along with our experience in overcoming them.
    Test Conference (ITC), 2013 IEEE International; 01/2013
  • Conference Proceeding: Best paper award winners
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: High computation is a predominant requirement in many applications. In this field, Graphic Processing Units (GPUs) are more and more adopted. Low prices and high parallelism let GPUs be attractive, even in safety critical applications. Nonetheless, new methodologies must be studied and developed to increase the dependability of GPUs. This paper presents effective fault mitigation strategies for CUDA-based GPUs against permanent faults. The methodology to apply these strategies, on the software to be executed, is fully described and verified. The graceful performance degradation achieved by the proposed technique outperforms multithreaded CPU implementation, even in presence of multiple permanent faults.
    Test Conference (ITC), 2013 IEEE International; 01/2013
  • [show abstract] [hide abstract]
    ABSTRACT: As scan compression becomes ubiquitous, ever more complex designs require higher compression. This paper presents a novel, two-level compression system for scan input data generated by deterministic test generation. First, load care bits and X-control input data are encoded into PRPG seeds; next, seeds are selectively shared for further compression. The latter exploits the hierarchical nature of large designs with tens or hundreds of PRPGs. The system comprises a new architecture, which includes a simple instruction-decode unit, and new algorithms embedded into ATPG. Results on large industrial designs demonstrate significant data and cycle compression increases while maintaining test coverage and performance.
    Test Conference (ITC), 2013 IEEE International; 01/2013
  • [show abstract] [hide abstract]
    ABSTRACT: Read and write assist techniques are widely adopted to allow voltage scaling in low-power SRAMs. In particular, this paper analyzes two assist techniques: word line level reduction and negative bit line boost. The analyzed assist techniques improve read stability and write margin of core-cells when the SRAM operates at a lowered supply voltage. In this work, we investigate the impact of such assist techniques on the faulty behavior of low-power SRAMs. This analysis is based on extensive injection of resistive-open and resistive-bridging defects in core-cells of a commercial low-power SRAM. Our study determines the most stressful configuration of assist circuits to detect each faulty behavior induced by injected defects. We show that, by applying most stressful configurations of assist circuits during test phase, defect coverage can be increased up to 89% w.r.t. test solutions that do not exploit assist circuits. Based on this analysis, we present an efficient test solution that exploits the configuration of assist circuits as a parameter to maximize the detection of studied defects, while reducing time complexity up to 73% w.r.t. test flows using state-of-the-art test algorithms.
    Test Conference (ITC), 2013 IEEE International; 01/2013
  • [show abstract] [hide abstract]
    ABSTRACT: A realistic, as opposed to fixed pessimistic end-of-life method to identify paths that are at-risk to excessive degradation due to aging is presented. It uses library cell grading information to assess the cells/instances for their sensitivity to parametric degradation.
    Test Conference (ITC), 2013 IEEE International; 01/2013
  • [show abstract] [hide abstract]
    ABSTRACT: Practical techniques for generating test signals between 10Gbps and 50Gbps are described. An historical review shows that the problem of extending ATE to higher rates has been around for several decades, with ever-increasing speed requirements. We demonstrate, in this paper that multiplexing techniques that permitted 40-50 Mbps testing in the 1980s (then using 10-20MHz ATE) can be applied to the present problem of achieved 1000x faster rates today (40-50Gbps). Some intervening steps are shown that achieved 5-10Gbps, and recently 12-24Gbps. These are extended to demonstrate synthesis of signals between 40 and 50Gbps. The paper is intended to aid others who might face similar challenges in testing high-end products prior to the day when 50Gbps ATE becomes common-place.
    Test Conference (ITC), 2013 IEEE International; 01/2013

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