IEEE International Test Conference (TC)

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ISSN 1089-3539

Publications in this journal

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    ABSTRACT: Through-silicon vias (TSVs) are crucial elements of 3-D bonded integrated circuits. Since they connect different layers of 3-D stacks, their proper operation is an essential prerequisite for the system function. This paper describes a procedure for deriving fault diagnosis test sequences to identify single and multiple defective TSVs. Additional experimental results obtained for pseudorandom patterns illustrate feasibility and robustness of the proposed test schemes in terms of their detection and diagnostic capabilities and are reported herein.
    IEEE International Test Conference (TC) 09/2013; DOI:10.1109/TEST.2013.6651894
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    ABSTRACT: In this paper, we will present two different applications of “test pattern sampling” for logic testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The drivers and implementations for these two methods were completely different - one relying on real-time analysis/optimization applied at wafer test; the other based on off-line analysis with daily updates and real-time adjustments at Final Test.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: In this paper, we present a new scan-path structure for improving the security of systems including scan paths, which normally introduce a security critical information leak channel into a design. Our structure, named differential scan path (DiSP), divides the internal state of the scan path in two sections. During the shift-out operation, only subtraction of the two sections is provided. Inferring the internal state from this subtraction requires much guesswork that increases exponentially with scan path length while the resulting fault coverage is only marginally altered. Subtraction does not preserve parity, thus avoiding attacks using parity information. The structure is simple, needs little area and does not require unlocking keys. Through implementing the DiSP in an elliptic curve crypto-graphic coprocessor, we demonstrate how easily it can be integrated into existing design tools. Simulations show that test effectiveness is preserved and that the internal state is effectively hidden.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: Parallel programming is an attractive solution to accelerate test pattern generation (TPG); however, the associated non-determinism often leads to non-reproducible test pattern sets. In this paper, the circular pipeline processing (CPP) principle is proposed to facilitate deterministic parallel TPG. CPP preserves the task processing orders that are necessary to ensure TPG determinism with low inter-thread synchronization overhead. Based on CPP, a deterministic parallel test pattern generator is developed; it guarantees to produce the same test pattern set regardless of the thread timing and the thread count. Experimental results on benchmark circuits show that the proposed test pattern generator exhibits close-to-linear speedup for at least up to 12 threads.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: Test time controls the competitiveness and viability of new precision products in two fundamental ways: it determines final test cost which is a major part of the recurring manufacturing cost, and it determines characterization test time which directly adds to time to market. This paper introduces a new test strategy aimed at dramatically reducing test time for precision analog and mixed signal products. The strategy is termed SATOM for Simultaneous AC-DC Test with Orthogonal Multi-excitations. In SATOM, a device under test is excited with multiple mutually-orthogonal stimulus signals that are simultaneously applied at different input points of the device. A single set of response data is acquired and an intelligent processing algorithm is used to simultaneously compute multiple AC and DC test specifications for the device. This results in a reduction of well over 90% in test time for those specs, with no negative impact on test coverage and test accuracy. Extensive measurement results demonstrated effectiveness, efficiency and robustness of the new method.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: Due to the current hardware and testing environment limitations, sometimes a perfect coherent condition cannot be satisfied regarding Digital-to-Analog Converter testing. In this paper, the existing algorithms for non-coherent sampling are reviewed and the limitations of each algorithm are analyzed. Then an enhanced procedure is proposed with detail explanation. The experimental results show the new procedure has a higher accuracy and a broader coverage.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: The paper describes clock gating structures in practice that can impact the testability and cause silicon failure due to the race condition or timing uncertainty such as voltage droop and the process variations. The design rule check (DRC) algorithm is presented to efficiently and robustly identify such problematic structures. Furthermore, the automatic test pattern generation (ATPG) method is proposed to handle the design with such rule violations to prevent simulation mismatches while minimizing the test coverage lost.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: The paper discusses practical issues involved in applying scan bandwidth management to large industrial system-on-chip (SoC) designs deploying embedded test data compression. These designs pose significant challenges to the channel bandwidth management methodology itself, flow, and tools. The paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with EDT-based test data compression. Moreover, some recently proposed SoC test scheduling algorithms are refined accordingly by making provision for (1) setting up test configurations minimizing test time, (2) optimization of SoC pin allocation based on scan data volume, and (3) handling physical constraints in realistic applications. Detailed presentation of a case study is illustrated with a variety of experiments that allow one to learn how to tradeoff different architectures and test scheduling.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: In high speed data communications, timing jitter and voltage noise analyses often depend on mathematical models to predict long-term reliability of the system, typically merited by a low bit error ratio (BER). Many methods involve the extrapolation of random jitter (RJ) and random noise (RN) to very low BER, assuming that RJ is white Gaussian noise. In reality, RJ spectra are not always white. Thus, RJ statistical distributions can deviate from an ideal Gaussian, affecting the accuracy of extrapolations. This paper presents a theory and model for relating RJ distributions with colored spectra. We apply this model to various filtered RJ spectra, including the extreme case of Brownian (1/f2) noise, and show correlation between simulation and measurement.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: Without appropriate stitching of scan chains, even with good diagnosis algorithm and diagnostic pattern generation, it may still result in bad scan chain diagnostic resolution. To improve the diagnostic resolution, we propose a novel Diagnosis and Layout Aware (DLA) scan chain stitching method, which is pattern independent and supports embedded scan compaction. It is based on three ideas: (1) increasing the number of sensitive scan cells, which can capture useful diagnostic information; (2) properly distributing the sensitive scan cells along the scan chains to enhance the overall resolution; (3) stitching scan cells based on their placement at layout to preserve the chip performance. Experiments on ISCAS'89/ITC'99 benchmark circuits and a real industry circuit based on 20nm technology with silicon results show that, the proposed DLA scan chain stitching method effectively improves the resolution, with negligible impact on chip performance, embedded scan compaction, transition fault coverage, and test power dissipation. The silicon results even show 7X average resolution improvement comparing to without using the proposed method.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: This paper describes our deployment of data mining techniques during final test to predict system level test failures and customer returns for two recent mixed-signal system-on-chip products. Emphasis is put on practical considerations for simplifying test flow implementation while still meeting the twin goals of reduced test cost and improved product quality.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    Conference Paper: Best paper award winners
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: With shrinking geometries of PCBs, increasing interface speeds and corresponding loss of test point access to diagnose structural test defects, new standard test mechanisms are needed to test chip-to-chip connectivity and functionality at the board level. New requirements for an integrated circuit 'BA' (Board-Assist) BIST to structurally test these interfaces will be presented. A standardized BA-BIST template and algorithms for industry leverage are proposed.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: As the supply chain of electronic circuits grows more complex, with parts coming from different suppliers scattered across the globe, counterfeit integrated circuits (ICs) are becoming a serious challenge which calls for immediate solutions. Counterfeiting includes re-labeling legitimate chips or illegitimately replicating chips and deceptively selling them as made by the legitimate manufacturer, or simply selling fake chips. Counterfeiting also includes providing defective parts or simply previously used parts recycled from scrapped assemblies. Obviously, there is a multitude of legal and financial implications involved in such activities and even if these devices initially work, they may have reduced lifetime and may pose reliability risks. In this tutorial, we provide a comprehensive review of existing techniques which seek to prevent and/or detect counterfeit integrated circuits. Various approaches are discussed and an advanced machine learning-based method employing parametric measurements is described in detail.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: In this summary paper, we discuss two types of sensors that provide a built-in test solution for RF circuits. The key characteristic of the sensors is that they are non-intrusive, in the sense that they are not electrically connected to the RF circuit under test. This has the important advantage that the design of the RF circuit becomes totally independent from the design of the sensors. In other words, the RF circuit design methodology and performance trade-offs are totally transparent to the insertion of the built-in test strategy. In particular, we propose variation-aware sensors to implement an implicit functional test and a temperature sensor to implement a defect-oriented test. The proposed sensors provide DC or low-frequency measurements, thus they have the potential to reduce drastically the test cost. We discuss the principle of operation of the sensors, we provide design guidelines, and we demonstrate the concept on a set of fabricated chips. To the best of our knowledge, this is the first proof-of-concept of RF test based on non-intrusive sensors.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: The requirements for the recent mobile devices are significantly different from those for the conventional PC-oriented devices in many aspects: power consumption, performance and production ramp-up speed. These unique requirements have created many challenges in process technology, design, and manufacturing. Mobile devices are battery-sensitive, but still need the horsepower to run performance-hungry applications. We need a very tight DTCO (Design and Technology Co-Optimization), and a steep production ramp with high yield. Samsung Electronics has been focusing on the development and manufacturing of mobile devices for many years. The unique challenges associated with mobile devices will be addressed in the talk, along with our experience in overcoming them.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: A conventional wafer sort test on an automatic test equipment (ATE) uses a fixed synchronous clock period. Typical test cycles may produce high signal activity and to keep the power dissipation under control, a relatively slow test clock is used. This results in long test times, especially for large scan based circuits. Observing that each test clock cycle may consume different amount of power, we propose an asynchronous clock test methodology to reduce the test time. Smallest customized clock periods for test cycles or sets of cycles are computed based on power and critical path constraints. A theoretical analysis shows that the total energy consumed by the entire test is invariant and the test time depends on the rate it is dissipated during test. An asynchronous clock test dissipates this energy at the maximum allowable rate, while the conventional synchronous clock test dissipates it at a lower average rate. The asynchronous clock test method is first implemented in simulation using several ISCAS'89 benchmark circuits. These results show test time reductions up to 47%. To establish the test programming feasibility of the new methodology the Advantest T2000GS ATE at Auburn University Test Lab was used. Test time reduction of 38% is demonstrated for scan test of a circuit. The paper ends with an investigation showing that for a circuit under test, given its power budget and a test there exists a supply voltage that minimizes the test time. An analysis determines whether the shortest test must use a synchronous or an asynchronous clock.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: System On a Chip and other highly integrated mixed signal devices have exploded in design and function complexity. New device designs exhibit non-determinism in timing, phase and data; functional blocks without a coherent shared time base; and the integration of many differing protocols and external busses. Traditional semiconductor ATE addresses these challenges with stored stimulus and response vectors and pre-planned timing, greatly increasing the difficulty of debug, lowering development productivity and reducing test coverage. The challenge is further extended by multi-site and concurrent test. Recent ideas in the development of protocol aware test methods and architectures promise to meet these challenges and introduce a new paradigm for test development. This paper will present an implementation of these ideas in a new digital channel architecture and demonstrate their application in a complete mixed signal SOC semiconductor ATE design.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: Running at-speed functional tests has shown to be a very effective method to detect faulty chips. In our previous paper we presented a methodology for generating functional tests aimed at hard to detect gate level faults in the control logic of a processor. In that methodology gate level tests were mapped to the register transfer level (RTL) and a faulty RTL model was built. The propagation constraints of the fault through the design were captured as linear temporal logic (LTL) properties. These constraints reduced the search space. Further, the constraints also allowed us to do structural reductions like cone of influence reduction and removal of irrelevant duplicated signals. Overall the constraints provided improved scaling. Not all the design behaviours are required to generate a test for a fault. In this paper we use this insight to scale our previous methodology further. Under-approximations are design abstractions that only capture a subset of the orignial design behaviors. The use of RTL for test generation affords us two types of under-approximations: bit-width reduction and operator approximation. Our experiments show that the use of these two under-approximations can achive 2× to 3× reduction in test generation time without compromising the fault coverage.
    Test Conference (ITC), 2013 IEEE International; 01/2013