IEEE International Test Conference (TC)

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  • ISSN
    1089-3539

Publications in this journal

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    ABSTRACT: Through-silicon vias (TSVs) are crucial elements of 3-D bonded integrated circuits. Since they connect different layers of 3-D stacks, their proper operation is an essential prerequisite for the system function. This paper describes a procedure for deriving fault diagnosis test sequences to identify single and multiple defective TSVs. Additional experimental results obtained for pseudorandom patterns illustrate feasibility and robustness of the proposed test schemes in terms of their detection and diagnostic capabilities and are reported herein.
    IEEE International Test Conference (TC) 09/2013;
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    ABSTRACT: The paper describes clock gating structures in practice that can impact the testability and cause silicon failure due to the race condition or timing uncertainty such as voltage droop and the process variations. The design rule check (DRC) algorithm is presented to efficiently and robustly identify such problematic structures. Furthermore, the automatic test pattern generation (ATPG) method is proposed to handle the design with such rule violations to prevent simulation mismatches while minimizing the test coverage lost.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: Without appropriate stitching of scan chains, even with good diagnosis algorithm and diagnostic pattern generation, it may still result in bad scan chain diagnostic resolution. To improve the diagnostic resolution, we propose a novel Diagnosis and Layout Aware (DLA) scan chain stitching method, which is pattern independent and supports embedded scan compaction. It is based on three ideas: (1) increasing the number of sensitive scan cells, which can capture useful diagnostic information; (2) properly distributing the sensitive scan cells along the scan chains to enhance the overall resolution; (3) stitching scan cells based on their placement at layout to preserve the chip performance. Experiments on ISCAS'89/ITC'99 benchmark circuits and a real industry circuit based on 20nm technology with silicon results show that, the proposed DLA scan chain stitching method effectively improves the resolution, with negligible impact on chip performance, embedded scan compaction, transition fault coverage, and test power dissipation. The silicon results even show 7X average resolution improvement comparing to without using the proposed method.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: In this paper, we will present two different applications of “test pattern sampling” for logic testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The drivers and implementations for these two methods were completely different - one relying on real-time analysis/optimization applied at wafer test; the other based on off-line analysis with daily updates and real-time adjustments at Final Test.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: Due to the current hardware and testing environment limitations, sometimes a perfect coherent condition cannot be satisfied regarding Digital-to-Analog Converter testing. In this paper, the existing algorithms for non-coherent sampling are reviewed and the limitations of each algorithm are analyzed. Then an enhanced procedure is proposed with detail explanation. The experimental results show the new procedure has a higher accuracy and a broader coverage.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: IEEE P1687 is a valuable tool for accessing on-chip instruments during test, diagnosis, debug, and board configuration. However, most of these instruments should not be available to an end user in the field. We propose a method for hiding instruments in a P1687 network that utilizes a “locking” segment insertion bit (LSIB) that can only be opened when pre-defined values, corresponding to a key, are present in particular bits in the chain. We also introduce “trap” bits, which can further reduce the effectiveness of brute force attacks by permanently locking an LSIB when an incorrect value is written to the trap's update register. Only a global reset will allow the LSIB to become operable again. In this paper, we investigate the cost and effectiveness of LSIBs and traps in several different configurations and show that these relatively small modifications to the P1687 network can make undocumented instrument access exceedingly difficult.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: SNR enhancement of a 6-band WCDMA/ HSDPA+ directconversion transceiver supporting 21 Mbps High Speed Downlink Packet Access Evolved (HSDPA+) in a single CMOS die is evaluated in this paper. The paper mainly focuses on enhancing SNR performance of a WCDMA/HSDPA+ receiver by minimizing the error vector magnitude (EVM) with the digital compensations of the amplitude and group delay variations of the analog channel selection filter, and bandwidth optimization in the cases of the absence and presence of the adjacent channel interferers (ACIs). The measurement results show that the receiver achieves RX EVM below 3% and 4%, respectively, for WCDMA QPSK and HSDPA+ 64-QAM signals across a very wide input signal power range in all bands, and negligible SNR degradation in the presence of the ACIs.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: In this paper we present a self-test method for RF transceivers to determine IQ imbalance, time skews, IIP3, IIP5, AM/AM, and AM/PM distortion with no hardware overhead. The analysis is done through the loop-back set-up over two frames, each of which is 200us in duration. The overall measurement time is less than 10ms including the computation time. The determined parameters can be used for digital calibration, which greatly enhances reliability and yield by widening the tolerance of the parameters. We show through hardware measurements that the target performance parameters can be determined accurately and the EVM can be reduced more than 5 folds, making even highly impaired systems usable. The only additional component to enable our approach is an attenuator in the loop-back path, which can be placed outside the chip. Hence, we call this self test and calibration approach a zero overhead approach.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: Recently, there is an increasing need for methods of functionally testing RF devices to provide lower cost alternatives to testing RF communication systems. In this paper, a real-time functional testing method of RF-ICs using a digital tester is proposed as an alternative to conventional RF testing. The method is based on a concept of direct modulation. By employing the proposed method, the QPSK and 16-QAM signals can be generated with digital tester drivers. The method can directly compare the baseband data with its expected data through digital tester comparators without demodulation. Therefore, the proposed method does not require any modulator or demodulator. Moreover, the method can perform both a stress test of RF receivers by injecting modulation error and a margin test of RF transmitters by using a dual-threshold comparator.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: New methods are proposed to guide line justification and fault propagation in test generation procedures to derive compact test sets. Experiments on several industrial designs yielded, on average, 24% reduction in test set sizes.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: Fault diagnosis of Integrated Circuits (ICs) has grown into a special field of interest in the Semiconductor Industry. Fault diagnosis is very useful at the design stage for debugging purposes, at high-volume manufacturing for obtaining feedback about the underlying fault mechanisms and improving the design and layout in future IC generations, and in cases where the IC is part of a larger safety-critical system (e.g. automotive, aerospace) for identifying the root-cause of failure and for applying corrective actions that will prevent failure reoccurrence and, thereby, will expand the safety features. In this summary paper, we present a methodology for fault modeling and fault diagnosis of analog circuits based on machine learning. A defect filter is used to recognize the type of fault (parametric or catastrophic), inverse regression functions are used to locate and predict the values of parametric faults, and multi-class classifiers are used to list catastrophic faults according to their likelihood of occurrence. The methodology is demonstrated on both simulation and high-volume manufacturing data showing excellent overall diagnosis rate.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: Wide I/O poses serious challenges due to the requisite high density of electronics and relays near the DUT, as well as high bandwidth. A 2×2mm MEMS switch has been demonstrated, offering >80% footprint reduction relative to a typical TO-can electromagnetic relay. A further benefit of its small size, the MEMS relay is able to operate up to Ka-band (40 GHz) with hot switch capability and repeatability of
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: This paper describes our deployment of data mining techniques during final test to predict system level test failures and customer returns for two recent mixed-signal system-on-chip products. Emphasis is put on practical considerations for simplifying test flow implementation while still meeting the twin goals of reduced test cost and improved product quality.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: Test time controls the competitiveness and viability of new precision products in two fundamental ways: it determines final test cost which is a major part of the recurring manufacturing cost, and it determines characterization test time which directly adds to time to market. This paper introduces a new test strategy aimed at dramatically reducing test time for precision analog and mixed signal products. The strategy is termed SATOM for Simultaneous AC-DC Test with Orthogonal Multi-excitations. In SATOM, a device under test is excited with multiple mutually-orthogonal stimulus signals that are simultaneously applied at different input points of the device. A single set of response data is acquired and an intelligent processing algorithm is used to simultaneously compute multiple AC and DC test specifications for the device. This results in a reduction of well over 90% in test time for those specs, with no negative impact on test coverage and test accuracy. Extensive measurement results demonstrated effectiveness, efficiency and robustness of the new method.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: In this paper, we present a new scan-path structure for improving the security of systems including scan paths, which normally introduce a security critical information leak channel into a design. Our structure, named differential scan path (DiSP), divides the internal state of the scan path in two sections. During the shift-out operation, only subtraction of the two sections is provided. Inferring the internal state from this subtraction requires much guesswork that increases exponentially with scan path length while the resulting fault coverage is only marginally altered. Subtraction does not preserve parity, thus avoiding attacks using parity information. The structure is simple, needs little area and does not require unlocking keys. Through implementing the DiSP in an elliptic curve crypto-graphic coprocessor, we demonstrate how easily it can be integrated into existing design tools. Simulations show that test effectiveness is preserved and that the internal state is effectively hidden.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: Parallel programming is an attractive solution to accelerate test pattern generation (TPG); however, the associated non-determinism often leads to non-reproducible test pattern sets. In this paper, the circular pipeline processing (CPP) principle is proposed to facilitate deterministic parallel TPG. CPP preserves the task processing orders that are necessary to ensure TPG determinism with low inter-thread synchronization overhead. Based on CPP, a deterministic parallel test pattern generator is developed; it guarantees to produce the same test pattern set regardless of the thread timing and the thread count. Experimental results on benchmark circuits show that the proposed test pattern generator exhibits close-to-linear speedup for at least up to 12 threads.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: In high speed data communications, timing jitter and voltage noise analyses often depend on mathematical models to predict long-term reliability of the system, typically merited by a low bit error ratio (BER). Many methods involve the extrapolation of random jitter (RJ) and random noise (RN) to very low BER, assuming that RJ is white Gaussian noise. In reality, RJ spectra are not always white. Thus, RJ statistical distributions can deviate from an ideal Gaussian, affecting the accuracy of extrapolations. This paper presents a theory and model for relating RJ distributions with colored spectra. We apply this model to various filtered RJ spectra, including the extreme case of Brownian (1/f2) noise, and show correlation between simulation and measurement.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: The paper discusses practical issues involved in applying scan bandwidth management to large industrial system-on-chip (SoC) designs deploying embedded test data compression. These designs pose significant challenges to the channel bandwidth management methodology itself, flow, and tools. The paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with EDT-based test data compression. Moreover, some recently proposed SoC test scheduling algorithms are refined accordingly by making provision for (1) setting up test configurations minimizing test time, (2) optimization of SoC pin allocation based on scan data volume, and (3) handling physical constraints in realistic applications. Detailed presentation of a case study is illustrated with a variety of experiments that allow one to learn how to tradeoff different architectures and test scheduling.
    Test Conference (ITC), 2013 IEEE International; 01/2013
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    ABSTRACT: Read and write assist techniques are widely adopted to allow voltage scaling in low-power SRAMs. In particular, this paper analyzes two assist techniques: word line level reduction and negative bit line boost. The analyzed assist techniques improve read stability and write margin of core-cells when the SRAM operates at a lowered supply voltage. In this work, we investigate the impact of such assist techniques on the faulty behavior of low-power SRAMs. This analysis is based on extensive injection of resistive-open and resistive-bridging defects in core-cells of a commercial low-power SRAM. Our study determines the most stressful configuration of assist circuits to detect each faulty behavior induced by injected defects. We show that, by applying most stressful configurations of assist circuits during test phase, defect coverage can be increased up to 89% w.r.t. test solutions that do not exploit assist circuits. Based on this analysis, we present an efficient test solution that exploits the configuration of assist circuits as a parameter to maximize the detection of studied defects, while reducing time complexity up to 73% w.r.t. test flows using state-of-the-art test algorithms.
    Test Conference (ITC), 2013 IEEE International; 01/2013