Proceedings of the International Workshop on Rapid System Prototyping Journal Impact Factor & Information

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ISSN 1074-6005

Publications in this journal

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    ABSTRACT: This paper presents a distributed hardware/software cosimulation environment for heterogeneous systems prototyping applied to an industrial application. The environment provides following features: distributed Hw/Sw cosimulation, automatic Hw/Sw interface generation, Hw elements can be described at different levels of abstraction and generic/specific Sw debuggers can be used. Starting from a brief description of the interface of the interconnected modules the tool automatically produces the link between Hw and Sw parts. In addition, the environment is very easy to use, even for complex systems that may include several Sw (C) modules and several Hw (VHDL) modules running in parallel. Applied to a large industrial multi-processor system, this method appeared reliable and efficient, providing important benefits in hardware-software codesign: better design environment and reduced time to validate.
    Proceedings of the International Workshop on Rapid System Prototyping 02/2013; 7(1):72-77. DOI:10.1109/IWRSP.1996.506730
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    ABSTRACT: Synthesis and Characterisation of hydrophobic polymer, for depollution of contaminated water by inorganic and organic chemicals
    Proceedings of the International Workshop on Rapid System Prototyping 01/2012; proceeding LASS.
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    ABSTRACT: Cache tuning has been shown to achieve considerable energy savings and methods have also been proposed for tuning the cache for standalone embedded applications. However, with the increasing complexity of modern day embedded applications, RTOS based multitasking systems are fast becoming the norm. Therefore, there exists a need for techniques to tune the cache for multitasking systems. In this paper we present a framework for energy centric tuning of the instruction cache for embedded multitasking systems. Our framework is built upon a formal model for characterizing multitasking systems and is suitable for fast instruction cache tuning using loop profiling. We validate our proposed techniques by applying them to tune a predictor based filter cache hierarchy - a common solution for low power embedded systems. For all the multitasking programs tested, our techniques are able to successfully predict configurations that are optimal or near-optimal. The proposed methods are also able to achieve speed-ups of up to an order of magnitude compared to exhaustive design space exploration techniques.
    Proceedings of the International Workshop on Rapid System Prototyping 01/2010; 4:439-457. DOI:10.1109/RSP.2009.16
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    ABSTRACT: Safety and comfort applications are addressed using driver assistance (DA) systems like adaptive cruise control (ACC) system using long range radar (LRR) or short range radar (SRR) or both. Novel waveforms and functionalities applied to next generation DA multi-sensor systems and their corresponding complex algorithms require advanced digital hardware supporting high computation rate and severe real-time constraints. In this paper, we present a flexible FPGA-based architecture for digital control and signal processing of a DA system. The considered DA system makes use of a new particular waveform to enhance capabilities of old generation ACC radar. Hardware/software partitioning has been explored in order to match the real-time requirement of the system. Development steps, from algorithm specification to on-board demonstration, are detailed. Promising results in terms of resources use and execution time are shown using a prototyping board with a single Virtex-II Pro device.
    Rapid System Prototyping, 2009. RSP '09. IEEE/IFIP International Symposium on; 07/2009
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    ABSTRACT: Ultra wideband (UWB) is considered to be the next major step on wireless technologies. This is due to its high data throughput which is combined with low power consumption since it is optimized for short distances. This paper presents the first, to the best of our knowledge, implementation of the digital signal processing module of the UWB transmitter, on a single state-of-the-art FPGA device, supporting even the highest mandatory transmission speeds. The presented design is based on the Multi-band OFDM physical (PHY) layer proposal, prepared by the IEEE 802.15.3a working group.We present the architecture of the system as well as the implementation results for various FPGA devices. We also explore the performance achieved by our architecture when implemented in different reconfigurable devices and we propose a high-end solution for maintaining the full data rates of UWB.
    Rapid System Prototyping, 2009. RSP '09. IEEE/IFIP International Symposium on; 07/2009
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    ABSTRACT: Rapid emergence of diverse wireless communication standards implies two crucial requirements on hardware mplementation: (1) Hardware platform flexibility for multistandard support, and (2) Rapid prototyping methodology for system validation under different use case scenarios. ASIP based platform, designed through architecture description language (ADL) fulfills both of these requirements in an elegant way. This paper presents the design summary and prototyping flow of an ASIP-based flexible MMSE-IC linear equalizer for MIMO turbo-equalization applications. The rapid development and prototyping flow has been described starting from LISA ADL description till the FPGA implementation.Using a logic emulation board integrating Virtex 5 FPGA, the prototype of 2 times 2 spatially multiplexed MIMO system achieves a throughput of 65 Msymbol/Sec at a clock frequency of 130 MHz.
    Rapid System Prototyping, 2009. RSP '09. IEEE/IFIP International Symposium on; 07/2009
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    ABSTRACT: Photovoltaic (PV) simulators are indispensable for the operational evaluation of PV energy production system components (e.g. battery chargers, DC/AC inverters, etc.), in order to avoid the time-consuming and expensive field-testing process. In this paper, the development of a novel real-time PV simulator based on Field Programmable Gate Arrays (FPGAs), is presented. The proposed system consists of a Buck-type DC/DC power converter, which is controlled by an FPGA-based unit using the Pulse Width Modulation (PWM) principle. The system operator is able to define both the PV module type to be simulated and the environmental conditions under which the selected PV module operates. The proposed design method enhances the rapid system prototyping capability and enables the reduction of the power converter size and cost due to the high clock speed feature of the FPGA-based control unit. The experimental results indicate that, using the proposed method, the PV module current–voltage characteristics examined are reproduced with an average accuracy of 1.03%.
    Proceedings of the International Workshop on Rapid System Prototyping 07/2009; DOI:10.1016/j.mejo.2008.05.014
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    ABSTRACT: In recent years, there was a tendency towards heterogeneous systems. The main property of these systems is that communication resources and computation resources are non-uniform in architecture and performance. Often,communication links between physically close infrastructure nodes provide high performance, e.g. in the sense of low latency or high bandwidth. A placement methodology for such systems should minimise the overall communication costs and prevent blocking of long, low-performanced communication links. Therefore application components with higher communication demands should be located closer to each other. For this, we propose a placement methodology that is based on a hierarchical application and infrastructure description. Due to our hierarchical approach, no knowledge about the potentially complex semantics of multi-dimensional communication demands is needed for the optimisation during the run-time of the placement. Our implementation shows a simple but efficient online-placement which also leads to a higher robustness in distributed embedded systems.
    Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, Shortening the Path from Specification to Prototype, RSP 2009, Paris, France, 23-26 June 2009; 01/2009
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    ABSTRACT: The increasing complexity of system-on-chip design - especially the software part of those systems - has stimulated much research work on design space exploration at the early stages of system development. In this paper we propose a new methodology for system modeling based on a specific UML profile. It defines a high design abstraction level for modeling and analyzing hardware resource sharing between system elements. Additionally, a SystemC-based simulator is developed in order to simulate modeled systems and evaluate their performance. Due to the high level of abstraction, the developed simulator enables fast exploration of design solutions. First promising results are presented and discussed over a mobile platform for the 3GPP LTE protocol stack.
    Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, Shortening the Path from Specification to Prototype, RSP 2009, Paris, France, 23-26 June 2009; 01/2009
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    ABSTRACT: Current multimedia applications give birth to a I number of complex heterogeneous multiprocessor architectures with specific communication infrastructure designed to achieve their demanding requirements. To obtain higher computational power with these multi-processor system on chips (MPSoCs), it is possible to connect several of them together through a specific network fabric, supported by dedicated network processors, reaching complexity levels too high for the general application programmer to cope with. This paper describes a flexible and efficient software implementation of communication mechanisms for such architectures, which masks the complexity of the communication infrastructure to the application programmer.
    Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, Shortening the Path from Specification to Prototype, RSP 2009, Paris, France, 23-26 June 2009; 01/2009
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    ABSTRACT: This paper presents a method for designing SystemC-compliant Instruction Set Simulators (ISS) that address three of the major problems system designers are faced with when modeling MP-SoCs architectures: the multiple levels of abstraction of the simulation models supporting the design space exploration, the simulation speed, and the debug of the multithreaded embedded application. First, this paper presents the ISS API and principles; then it describes how the same ISS can support SystemC simulation at several abstraction levels: untimed transaction level, approximately timed transaction level, and cycle accurate; then, it describes how the proposed ISS API has been used by six different laboratories - in the framework of the SoCLib project - to share the same L1 cache simulation model, and to wrap seven different processor cores in the same generic wrappers.Finally we demonstrate how the proposed API has been exploited to develop a generic debug and instrumentation infrastructure that can be used for all the processor cores, and all the abstraction levels supported by the SoCLib virtual prototyping platform.
    Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, Shortening the Path from Specification to Prototype, RSP 2009, Paris, France, 23-26 June 2009; 01/2009
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    ABSTRACT: Utilizing high level hardware description languages for the creation of customized circuits facilitates the rapid development and deployment of new hardware. While hardware design languages increase the speed at which hardware can be developed, creating hardware designs that are both efficient in resource usage and processing speed can be time consuming and require much experience. This problem is compounded more by the long design cycle times that are introduced by the long compilation and synthesis times that are required to translate a high level hardware description language to a circuit. This problem is addressed by performing some of the optimizations automatically, pre-synthesis, reducing the total number of synthesis cycles that are required, saving much development time.
    Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, Shortening the Path from Specification to Prototype, RSP 2009, Paris, France, 23-26 June 2009; 01/2009
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    ABSTRACT: We address the problem of rapid development of complex real-time task-sets through a Model Driven De- velopment (MDD) approach. The task-set is specified according to the graphic formalism of timeline schemas and it is translated into C-code that implements the dynamic architecture of the task-set on top of Linux- RTAI operating system. The transformation is per- formed through an engine obtained as an instance of a new model-transformation framework based on Java and eXtensible Stylesheet Language Transformations (XSLT) called JComposer. This is designed according to a flexible architecture that enables agile evolution of specification formalisms and target artifacts employed along the development process.
    Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, Shortening the Path from Specification to Prototype, RSP 2009, Paris, France, 23-26 June 2009; 01/2009
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    ABSTRACT: In this paper a formal method is proposed, based on attribute grammars (AG), for rapid SoC prototyping. A generic platform is also proposed for the automatic SoC implementation of AG-based applications. The proposed system, given the specification of the application in the formalism of attribute grammars, automatically produces the necessary hardware modules for the syntactic and semantic analysis of input strings belonging to that grammar. The produced implementation tackles with the recognition task of the input string, using a hardware implementation of an extension of Earley's parallel parsing algorithm. Moreover, the system exhibits capabilities of inexactness. The attribute evaluation makes usage of a stack-based hardware. The hardware modules are described in Verilog Hardware Description Language (Verilog HDL) and synthesizedin a Xilinx Virtex-5 ML506 FPGA. For the illustration of the proposed system, an example from the area of hardware compilers is given.
    Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, Shortening the Path from Specification to Prototype, RSP 2009, Paris, France, 23-26 June 2009; 01/2009
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    ABSTRACT: The development of embedded software for high confidence systems is a challenging task that must be supported by a deep integration of control theoretical and computational aspects. Model-based development of embedded software has been practiced for more than a decade now,but very few integrated approaches have emerged to provide end-to-end support for the process, and integrate platform aspects as well as verification. The paper describes an early version of a model-based prototyping tool chain that provides such support and covers most engineering steps.The tool chain is coupled with a hardware-in-the-loop simulation system, allowing quick experimental evaluation of designs.
    Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, Shortening the Path from Specification to Prototype, RSP 2009, Paris, France, 23-26 June 2009; 01/2009