IEEE Transactions on Components Packaging and Manufacturing Technology Part B (IEEE Trans Compon Packag Manuf)

Publisher: Institute of Electrical and Electronics Engineers; Lasers and Electro-optics Society (Institute of Electrical and Electronics Engineers); Components, Packaging & Manufacturing Technology Society, Institute of Electrical and Electronics Engineers

Current impact factor: 0.00

Impact Factor Rankings

2015 Impact Factor Available summer 2016
2000 Impact Factor 0.828
1999 Impact Factor 0.904
1998 Impact Factor 0.49
1997 Impact Factor 0.433

Impact factor over time

Impact factor

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5-year impact 0.00
Cited half-life 0.00
Immediacy index 0.00
Eigenfactor 0.00
Article influence 0.00
Website IEEE Transactions on Components, Packaging, and Manufacturing website
Other titles IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging, Transactions on components, packaging, and manufacturing technology., Advanced packaging, Components, packaging, and manufacturing technology
ISSN 1070-9894
OCLC 28525078
Material type Periodical, Internet resource
Document type Journal / Magazine / Newspaper, Internet Resource

Publisher details

Institute of Electrical and Electronics Engineers

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Publications in this journal

  • [Show abstract] [Hide abstract]
    ABSTRACT: A new approach to dielectric material characterization with a vector network analyzer is presented. As the characteristic impedance (Z <sub>0</sub>) of a stripline transmission line can be accurately determined by measuring the two-port scattering parameters in the frequency range of interest, the dielectric constant of the insulation material that consists as part of the stripline configuration is then obtained by a relationship to the characteristic impedance. The dielectric loss (or loss tangent) can be determined by measuring the return loss and the insertion loss of the stripline. The validity of the technique is demonstrated for well-characterized dielectric materials such as Teflon-based and other composite laminates. The technique is then applied to integrated circuit (IC) molding compounds as-processed
    IEEE Transactions on Components Packaging and Manufacturing Technology Part B 12/1998; 21(4-21):441 - 446. DOI:10.1109/96.730427
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    ABSTRACT: Not Available
    IEEE Transactions on Components Packaging and Manufacturing Technology Part B 12/1998; 21(4):322-323. DOI:10.1109/TCPMB.1998.730411
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    ABSTRACT: In this study, the coefficient of thermal expansion (CTE) and the elastic modulus of epoxy molding compound (EMC) are measured using fabricated specimens and then the measured values are compared with the predicted values by theoretical equations (such as dilute suspension method, self consistent method, Hashin-Shtrikman's bounds, Shapery's bounds and others). The measured values are distributed within the upper and lower bounds of predicted values. The measured elastic modulus and the CTE of EMC approach close to the predicted values by self consistent method and upper bound of Shapery's equation respectively. Two-dimensional (2-D) and three-dimensional (3-D) finite element analysis are performed using the measured and analytically predicted values. Finite element method (FEM) analysis indicates that firstly the EMC with eighty weight percentage of filter shows less thermal stress when package is cooling down and relatively high thermal stress when package is heating up. Secondly the stress concentrations at the edge sections about two times higher than the interfaces and at the vertex parts about 1.4 times higher than the edge sections are observed
    IEEE Transactions on Components Packaging and Manufacturing Technology Part B 12/1998; 21(4-21):413 - 421. DOI:10.1109/96.730423
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    ABSTRACT: In our previous reports [see ibid., vols. 19/20, p, 593/176, 1996/1997], geometries of the delaminations which are most likely to lead to resin cracking in large scale integration (LSI) packages subjected to temperature cyclic loading were identified for both Cu alloy and alloy 42 leadframe packages. In this paper, assuming these delaminations, we conduct comprehensive numerical stress analysis of resin cracking to study the effect of properties of encapsulant resin and die-bonding materials and the package geometry factors. The impacts of these design parameters on resin cracking are determined and a package design guide is established
    IEEE Transactions on Components Packaging and Manufacturing Technology Part B 12/1998; 21(4-21):407 - 412. DOI:10.1109/96.730422
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    ABSTRACT: This paper will discuss multichip module technology as it is applied to a prototype high performance direct digitizing channelized radar receiver system under development for the Navy's E2-C Airborne Early Warning Aircraft, which encompasses both analog signals at UHF frequencies and multigigahertz digital signals. Critical issues which arise in the design of such a system will be discussed, including thermal management, transmission line design, design of power and ground distribution systems, and analyses of voltage standing wave ratio and simultaneous switching noise. This paper will describe in detail the simulations and analyses which were undertaken during the development of the multichip module containing the analog-to-digital converter and demultiplexer for this system. Finally, test results from measurements of analog-to-digital converter performance at the full operating clock rates of the multichip module will be described, along with lessons learned for the design of subsequent generations of these high performance mixed signal systems
    IEEE Transactions on Components Packaging and Manufacturing Technology Part B 12/1998; 21(4-21):447 - 462. DOI:10.1109/96.730428
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    ABSTRACT: This paper presents a modular architecture for a scalable ATM-switch. The cell routing function, as well as the associated queueing, are distributed over many small clusters of nodes, called basic modules. These basic modules are hierarchically interconnected to form larger switches. In a basic module, every node is interconnected with adjacent nodes in the same module with three of its four links. The fourth link is used to connect either to an external port or to other basic modules at higher levels of the hierarchy. From a hardware implementation perspective, the simplicity of the architecture stems from the fact that each node in the switch consists of two small crossbar switches of low complexity, a buffer, and a controller. The hierarchial nature of the topology allows for modular growth of the switch. Further, the interconnection topology of the switch makes it suitable for three-dimensional (3-D) (stacked VLSI) implementation
    IEEE Transactions on Components Packaging and Manufacturing Technology Part B 12/1998; 21(4-21):338 - 345. DOI:10.1109/96.730414
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    ABSTRACT: The effects of tin diffusion, silver and palladium dispersion, and intermetallic compound growth on the shear fatigue of solder joints between thick film mixed bonded conductor Pd-Ag and solder 62Sn-36Pb-2Ag are investigated. Microstructural analysis reveals that the intermetallic compounds (IMC's) Pd<sub>3</sub>Sn<sub>2</sub>, Pd<sub>3 </sub>Sn, Pd<sub>2</sub>Sn, Pd<sub>3</sub>Sn<sub>2</sub>, PdSn, PdSn<sub>2</sub>, PdSn<sub>4</sub>, Ag<sub>5</sub>Sn, Ag<sub>3</sub>Sn, PbPd<sub>3</sub>, and Pb<sub>3</sub>Pd<sub>5</sub> are formed after aging. X-ray dot maps demonstrate that the longer the aging time, the more serious the silver and palladium dispersion into the solder and the tin diffusion into the conductor. It is observed that the tin diffuses to the interface of the substrate/conductor after 120 h aging. Shear strength tests with different strain rate show that the adhesion strength decreases with prolongation of aging time. Shear cycling tests indicate that the fatigue lifetime of the solder joints depends on the diffusion depth of the silver and palladium, especially the tin diffusion into the thick film conductor. The above results mean that the more serious is the tin and silver interdiffusion, and the more IMC's are formed in the solder joint (effects which are the result of prolonged storage at high temperature or of long term operation in real SMT assemblies), the more sensitive is the solder joint to stress. Eventually fatigue failure of the joint may result. It is argued that volume change and increased brittleness caused by the intermetallic formation, and volume swelling of the conductor layer due to tin diffusion, are major factors in the decrease of fatigue lifetime and degradation of the shear strength of the solder joints
    IEEE Transactions on Components Packaging and Manufacturing Technology Part B 12/1998; 21(4-21):398 - 406. DOI:10.1109/96.730421
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    ABSTRACT: A simple chip-to-chip interconnect technique with adhesive bonded ribbons is presented. It solves the insertion loss problem of wire bond interconnects in micro- and millimeterwave assemblies. The following paper discusses design and fabrication of such interconnects. A quasistatic model is developed to ease the quality assessment of their electrical behavior. It is validated by measurements on microstrip resonators with and without interconnects. The chip-to-chip interconnect technique with adhesive bonded ribbons exhibit low loss and is useable up to 50 GHz or more
    IEEE Transactions on Components Packaging and Manufacturing Technology Part B 12/1998; 21(4-21):463 - 470. DOI:10.1109/96.730429
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    ABSTRACT: A study is made of the tendency of growth of delamination between dissimilar materials occurring in large scale integration (LSI) plastic packages under temperature cyclic loading. Two groups of delamination growth processes are considered; one along the interface between the top surface of the die pad and the die-bonding layer, and the other along the interface between the bottom surface of the die pad and the encapsulant resin. In each group several different initial patterns of delaminations are assumed. Stress intensity factors and their mode ratios at the tips of growing delaminations are calculated by combining a thermoelastic finite element method for nonlinear contact problems and a linear interface fracture mechanics approach. The effects of geometries of delamination and leadframe materials on the tendency of delamination growth are clarified
    IEEE Transactions on Components Packaging and Manufacturing Technology Part B 12/1998; 21(4-21):422 - 427. DOI:10.1109/96.730424
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    ABSTRACT: The advent of MEMS (microelectromechanical systems) will enable dramatic changes in semiconductor processing. MEMS-based devices offer opportunities to achieve higher performance and functionality, at lower cost, with decreased size and increased reliability. In this work, we describe the achievement of several important devices for use in the semiconductor equipment industry. They include a low-flow mass flow controller, a high-precision pressure regulator, and an integrated gas panel. Compared to current technology, the devices are ultra-small in size, thus minimizing dead volumes and gas contact surface areas. With wettable surfaces comprised of ceramic and silicon (or, silicon coated with Si3N4 or SiC), they are resistant to corrosion, and generate virtually no particles. The devices are created from modular components. The science and technology of these components will be detailed. The modules examined are: normally-open proportional valves; normally-closed, low leak-rate shut-off valves; critical orifices (to extract information of flow rate); flow models (to extract flow rate from pressure and temperature information); silicon-based pressure sensors; and, the precision ceramic-based packages which integrate these modules into useful devices for semiconductor processing. The work finishes with a detailed description of the low-flow mass flow controller.
    IEEE Transactions on Components Packaging and Manufacturing Technology Part B 12/1998; 21(4-21):352 - 359. DOI:10.1109/96.730416
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    ABSTRACT: We have developed plastic-molded receptacle-lope vertical-cavity surface-emitting laser (VCSEL)-array modules directly push/pull connectable with the one-dimensional (1-D) conventional mechanically-transferable multifiber push-on (MPO) fiber connector and with a new two-dimensional (2-D) MPO-compatible fiber connector developed for this module. The VCSEL was mounted on the plastic-molded package using a highly precise completely alignment-free process using flip-chip solder bonding and ball-guide die bonding. These modules exhibit an optical coupling loss of 0.67±0.23 dB (efficiency: 85.8±2.93%) and a loss deviation of less than 0.26 dB for 100 matings with the fiber connector (MMF50). The modules were operated at a bit rate of 1 Gbps/ch without an isolator and showed floorless bit error rate (BER) performance at temperatures up to 70°C. At 1 Gbps/ch their optical sensitivity at a BER of 10<sup>-11</sup> was -26.0 dBm±0.9 dB. These structures and techniques are applicable to high-density, high-throughput optical parallel interconnections and optical space-division switches
    IEEE Transactions on Components Packaging and Manufacturing Technology Part B 12/1998; 21(4-21):471 - 478. DOI:10.1109/96.730430
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    ABSTRACT: THE preceding list of eight papers have been selected from the 60 papers presented at the 6th IEEE Topical Meeting on Electrical Performance of Electronic Packaging, EPEP'97, which was held in San Jose, CA, on October 27–29, 1997. Attendance was up 20% compared to the previous year which is a strong indication of the growing concern with electrical performance issues. The meeting had a truly international participation with presenters and attendees from Korea, Japan, Germany, Belgium, Spain, Austria, and Hungary. The technical sessions addressed the latest developments in power distribution, modeling of noise sources in package structures and interconnects, characterization techniques for both digital and microwave applications, and accelerated modeling and simulation methods. Very good presentations were given by participants from both industry and universities. Six invited talks from IBM, SUN, and Vienna University of Technology were spread over the three days.
    IEEE Transactions on Components Packaging and Manufacturing Technology Part B 12/1998; 21(4):480-480. DOI:10.1109/TCPMB.1998.730431
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    ABSTRACT: The commonly used deposition technology for solder bumps (evaporation or electroplating) requires thin-film processing. The compatibility of the solder-wettable metallizations does not allow the use of the same production equipment as installed in the wafer-fabrication facility. In this study, a maskless bump process is described, Here, solder droplets are ejected from a capillary and impinge on wettable bond-pad metallizations of electroless-deposited Ni/P-Au. Droplets impinging on a rough surface layer often bounce away. It is shown that this roughness layer is mainly determined by the Zn nucleation on the bondpad metallizations. Nucleation conditions are optimized to deposit only small particles of the same size. The volume of the droplets depends on the product of pulse amplitude and pulse length. Degradation of the interconnection between the piezoelectric actuator and the glass capillary requires a larger pulse amplitude for stable jetting behavior. In addition, it is found that every first droplet on a new position is larger than all other droplets ejected directly thereafter. The diameter distribution of the latter are within the requirements for the final bump. The quality of the solder-jetted bump is studied by several reliability tests after flip-chip assembly on printed wiring boards (PWBs). In combination with underfill, the reliability of solder-jetted bumps are comparable with electroplated bumps
    IEEE Transactions on Components Packaging and Manufacturing Technology Part B 12/1998; 21(4-21):371 - 381. DOI:10.1109/96.730418