IEEE Transactions on Very Large Scale Integration (VLSI) Systems (IEEE T VLSI SYST)

Publications in this journal

• Article: Failure mitigation techniques for 1T-1MTJ spin-transfer torque MRAM bit-cells

  Xuanyao Fong, Yusung Kim, Sri Harsha Choday, Kaushik Roy
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 03/2013; PP(99):1-12.
• Article: Resistive Threshold Logic

  Alex Pappachen James, Linu Rose, Dinesh S Kumar
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 01/2013;
• Article: A Ultra High Speed 1-Bit Full-Adder Cell

  M. Sadeghi, A. Golmakani
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  ABSTRACT: The increasing demand for the high fidelity devices has laid emphasis on the development of high speed, low power and high performance systems. The 1-bit full-adder circuit is very important component in the design of application specific integrated circuits. This paper presents a novel ultra-high speed full-adder based on GDI, TG and pass-transistor techniques. The main advantage of this design is very low propagation delay, which leads to achieving lower PDP and EDP than others. In this design the Sum is designed using TG, GDI and pass-transistor techniques, and the Cout is designed utilizing Majority Function Technique. Intensive HSPICE simulation shows that the new full-adder consumes 28.6% less power than SS16T adder, moreover its propagation delay 48.6% less than SS16T full-adder. We have compared some of the most popular full-adder cells like 28T, CPL, SS16T, 14T with proposed full-adder .Simulation has been carried out by HSPICE in 0.18µm technology at 1.8V supply voltage.
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 01/2013; under review.
• Article: Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs

  Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 01/2013; 21(2):239-249.
• Article: Symbolic Moment Computation for Statistical Analysis of Large Interconnect Networks

  Zhigang Hao, Guoyong Shi, Sheldon X.-D. Tan, E. Tlelo-Cuautle
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  ABSTRACT: The shrinking technology feature size and dense large-scale integration make process variation a challenging issue directly confronting the latest design automation tools. Process variation causes severe variation in interconnect networks, including very large-scale integrated interconnect structures, such as clock trees, clock mesh, power-ground networks, and other wiring structures in 3-D integrated circuits. The traditional moment computation techniques are only partly useful for analyzing such variational problems, however, their computational efficiency cannot meet the quickly rising needs, such as statistical analysis. This paper presents a novel symbolic moment calculator (SMC) for variational interconnect analysis. The moment calculator is constructed in a regular data structure that incorporates binary decision diagrams for data storage and computation. Given an interconnect circuit, such a computation diagram has to be constructed only once and can be repeatedly invoked for computation of moments with varying parameter values. Also, the SMC is friendly to interconnect synthesis in that it can be incrementally modified according to the modifications made to the circuit structure. Applications of the SMC for fast moment computation, sensitivity analysis, and statistical timing analysis are addressed. Significant efficiency is demonstrated comparing to other existing methods.
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 01/2013;
• Article: Novel Structure of Multiplier with Ultra-Low Power

  M. Sadeghi, A. Golmakani
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  ABSTRACT: Multiplication is a vital function for practically and DSP system. In this paper is presented a novel structure of multiplier unit, which the main advantage this structure has the lowest adder unit count, consumption power, and propagation delay. In this paper is simulated some of common structures of multiplier by using 28T full adder cell. We have compared some of the most common multiplier structures like Array multiplier, RCA multiplier, Braun multiplier, Bypassing RCA, Bypassing CSA, and proposed structure of multiplier. Intensive HSPICE simulation shows that the new structure consumes 24.96% less power than Bypassing RCA multiplier, moreover its propagation delay and adder units count 36.15% and 16.66% lower than Bypassing RCA multiplier respectively. Simulation has been carried out by HSPICE in 0.18µm technology at 1.8V supply voltage.
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 01/2013; Under review.
• Article: Semi-Serial On-Chip Link Implementation for Energy Efficiency and High Throughput

  Ethiopia Nigussie, Sampo Tuuna, Juha Plosila, Jouini A. Isoaho, Hunnu A. Tenhunen
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  ABSTRACT: A high-throughput and low-energy semi-serial on-chip communication link based on novel design techniques and circuit solutions is presented. This self-timed link is designed using high-speed serialization/d eserializtion and pulse dual-rail encoding techniques. The link also employs wave-pipelined dif- ferential pulse current-mode signaling to maintain the high speed data intake from the serializer. The energy ef fi ciency of the pro- posed semi-serial link, which consis ts of bit-serial links in parallel, mainly comes from the sharing of the novel serializer’s control cir- cuit among the bit-serial links. In addition, the integration of pulse signaling with wave-pipelining, the use of a new low-complexity data validity detection technique, and the avoidance of data de- coding logic also contribute to the power reduction. Furthermore, the formulated pulse dual-rail e ncoding provides an opportunity to implement pulse signaling at no cost. The ability to detect data validity at bit level allows acknowledgment per word without losing the delay-insensitivity o f the transmission. The proposed semi-seriallinkisanalyzedandcomparedwithbit-serialandfully bit-parallel links for 64-bit data and communication distances of 1 to 8 mm. The semi-serial link which consists of eight bit-serial links provides 72.72 Gbps throughput with 286 fJ/bit energy dissi- pation for 8 mm transmission. It dissipates the lowest energy per bit compared to fully bit-parallel links while achieving the same throughput. The links are designed and simulated in Cadence Analog Spectre using 65-nm technology from STMicroelectronics.
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12/2012; 20(12):2265 - 2277.
• Article: A Failure Prediction Strategy for Transistor Aging

  Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11/2012; Vol. 20(No. 11):pp. 1951-1959.
• Article: Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization

  X Chen, Y Wang, Y Cao, Y Ma, H Yang
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11/2012; 20(11):2143-2147.
• Article: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling

  F. Crupi, M. Alioto, J. Franco, P. Magnone, B. Kaczer, G. Groeseneken, J. Mitard, L. Witters, T. Y. Hoffmann
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  ABSTRACT: In this paper, the potential of Silicon-Germanium (SiGe) technology for VLSI logic applications is investigated from a circuit perspective for the first time. The study is based on experimental measurements on 45-nm SiGe pMOSFETs with a high- κ/metal gate stack, as well as on 45-nm Si pMOSFETs with identical gate stack for comparison. In the reference SiGe technology, an innovative technological solution is adopted that limits the SiGe material only to the channel region. The resulting SiGe device merges the higher speed of the Ge technology with the lower leakage of the Si technology. Appropriate circuit- and system-level metrics are introduced to identify the advantages offered by SiGe technology in VLSI circuits. Analysis is performed in the context of next-generation VLSI circuits that fully exploit circuit- and system-level techniques to improve the energy efficiency through aggressive voltage scaling, other than low-leakage techniques. Analysis shows that the SiGe technology has more efficient leakage-delay and dynamic energy-delay trade-offs at nominal supply, compared to Si technology. Moreover, it is shown that the traditional analysis performed at nominal supply actually underestimates the benefits of SiGe pMOSFETs, since the speed advantage of SiGe VLSI circuits is further emphasized at low voltages. This demonstrates that SiGe VLSI circuits benefit from aggressive voltage scaling significantly more than Si circuits, thereby making SiGe devices a very promising alternative to Si transistors in next-generation VLSI systems.
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 08/2012; 20(8):1487-1495.
• Article: Modeling of Energy Dissipation in RLC Current-Mode Signaling

  S. Tuuna, E. Nigussie, J. Isoaho, H. Tenhunen
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 06/2012; 20(6):1146 - 1151.
• Article: Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes

  MM Wong, MLD Wong, AK Nandi, I Hijazin
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  ABSTRACT: n this work, we derive three novel composite field arithmetic (CFA) Advanced Encryption Standard (AES) S-boxes of the field GF(((22)2)2). The best construction is selected after a sequence of algorithmic and architectural optimization processes. Furthermore, for each composite field constructions, there exists eight possible isomorphic mappings. Therefore, after the exploitation of a new common subexpression elimination algorithm, the isomorphic mapping that results in the minimal implementation area cost is chosen. High throughput hardware implementations of our proposed CFA AES S-boxes are reported towards the end of this paper. Through the exploitation of both algebraic normal form and seven stages fine-grained pipelining, our best case achieves a throughput 3.49 Gbps on a Cyclone II EP2C5T144C6 field-programmable gate array.
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 06/2012; 20(6):1151-1155.
• Source

  Available from: virginia.edu

  Article: Enhancing NBTI Recovery in SRAM Arrays Through Recovery Boosting

  T. Siddiqua, S. Gurumurthi
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  ABSTRACT: Negative bias temperature instability (NBTI) is an important lifetime reliability problem in microprocessors. SRAM-based structures within the processor are especially susceptible to NBTI since one of the pMOS devices in the memory cell always has an input of “0”. Previously proposed recovery techniques for SRAM cells aim to balance the degradation of the two pMOS devices by attempting to keep their inputs at a logic “0” exactly 50% of the time. However, one of the devices is always in the negative bias condition at any given time. In this paper, we propose a technique called Recovery Boosting that allows both pMOS devices in the memory cell to be put into the recovery mode by slightly modifying to the design of conventional SRAM cells. We evaluate the circuit-level design of a physical register file and an issue queue that use such cells through SPICE-level simulations. We then conduct an architecture-level evaluation of the performance and reliability of using area-neutral designs of these two structures. We show that Recovery Boosting provides significant improvement in the static noise margins of the register file and issue queue while having very little impact on power consumption and performance.
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 05/2012;
• Source

  Available from: duke.edu

  Article: Physical-Defect Modeling and Optimization for Fault-Insertion Test

  Z. Zhang, Z. Wang, X. Gu, K. Chakrabarty
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  ABSTRACT: Hardware fault insertion is a promising method for system reliability assessment and fault isolation. It provides feedback on the fault tolerance of a large system, creates artificial faulty scenarios that can be used as reference points for fault diagnosis, and leads to a quality diagnostic program. Optimization of fault insertion location is critical for accelerating the assessment of system reliability and constructing a complete knowledge base for fault diagnosis. In this work, we construct a pin-level fault model that is able to effectively mimic the errors (effects) caused by physical defects within the component. A simulation framework and optimization techniques are proposed to select a minimum subset of output pins that can represent as many physical defects as possible. The optimization results provide guidelines on the fault insertion locations and the appropriate fault types for insertion. In addition, three intrinsic characteristics of output pins, including testability number, fan-in size, and transition counts, are analyzed. The effectiveness of the proposed model is evaluated in terms of impact on system response and error-detection latency. Experimental results are presented for OpenCore benchmarks.
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 05/2012;