# Microelectronics Journal

## Description

• Impact factor
0.91
• ISSN
0959-8324

## Publications in this journal

• ##### Article: A High O/P Resistance, Wide Swing and Perfect Current Matching Charge Pump having Switching Circuit for PLL
[hide abstract]
ABSTRACT: The charge pump (CP) circuit is one of the main building block in a phase-locked loop (PLL) based frequency synthesizers. In conventional CMOS charge pump circuits, there are some non-ideal effects such as clock feed through, current mismatch and charge sharing which result in a phase offset in phase-locked loop circuits. This paper presents a new charge pump circuit in 0.18 $\mu$m CMOS technology, which greatly reduces the mismatch of current between two branches of the cascode current mirror. By using this proposed architecture, the mismatching between the UP/DN current of the CP can be achieved with less than 0.065$\%$ from post-layout simulation. As a result the spur and also the overall phase noise of the PLL are reduced. The charge pump output voltage range is 0.40-1.25 V. Additionally, the proposed circuit has wide output voltage swing and high output resistance, which ensures its good performance under very low power supply. Further, this CP circuit is incorporated with a new switching circuit to eliminate the clock feed through and charge injection error.
Microelectronics Journal 06/2013; 44:9.
• ##### Article: Proposal and implementation of a new interpolation technique for a double folding A/D converter
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ABSTRACT: This proposal of a new interpolation technique is presented for application in a double folding A/D converter with interpolation. This interpolation technique is applied in the master latches of the A/D converter without consumption increase. Compared to resistive interpolation, this new interpolation technique has the advantage of avoiding the resistive interpolation ladder adding only three transistors in some master latches and the current is the same as in the simple master latch. A 6-bit A/D converter was designed and implemented in a 1.2 mm BiCMOS process, an FT of 8 GHz, to explain the implementation of interpolation circuitry and evaluate the experimental results.
Microelectronics Journal 02/2013; 30(12):1213-1219.
• ##### Article: Compact Modeling of TANOS Program/Erase Operations for SPICE-like Circuit Simulations
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ABSTRACT: We present an analytical model of TANOS program/erase transients that can be used to implement a compact SPICE-like model of these memory devices. Simulation results obtained from a physics-based TANOS model are used to derive simple analytical formulas relating the program/erase currents and the centroid of the trapped charge distribution to operating conditions and stack composition. The model allows reproducing with a good agreement the experimental program/erase transients, thus providing a valuable tool for IC designers to optimize TANOS memory circuits, especially in the framework of multi-level applications.
Microelectronics Journal 01/2013; 44(1):50.
• ##### Article: Deterministic solution of the 1D Boltzmann transport equation: Application to the study of current transport in nanowire FETs
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ABSTRACT: In this work we investigate the ballistic ratio and the backscattering coefficient in nanowire FETs operating under quasi-ballistic conditions. Starting from general expressions of the current–voltage characteristics worked out in a previous paper, we extract the above parameters and their functional dependence on inversion-layer charge and device length. The computation is based on a rigorous analytic solution of the BTE and on a numerical solution of the coupled Schrödinger–Poisson equations, by which multiple subbands are taken into account. We propose three different definitions of the ballistic ratio, clarify their meaning and compute their values against the gate voltage and the device length. As opposed to most phenomenological treatments addressing this subject for 2D nanoscale MOSFETs, the strength of our approach is that the aforementioned parameters can be computed from the knowledge of the scattering probabilities, without introducing any major simplifying assumptions.
Microelectronics Journal 01/2013;
• ##### Article: Fully digital jerk-based chaotic oscillators for high throughput pseudo-random number generators up to 8.77 Gbits/s
Microelectronics Journal 01/2013;
• ##### Article: Ultra low power dual-gate 6T and 8T stack forced CNFET SRAM cells
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ABSTRACT: In this paper, two ultra-low power Single Walled Carbon Nanotube Field-Effect Transistor (SWCNFET) based SRAM cells are proposed to minimize static power dissipation due to leakage. The proposed first cell consists of six transistors (6T) with dual-gate n-type CNFETs whose back gates are negatively biased and the second cell employs stack forcing in the pull down n-type transistors of the cell, resulting in a symmetric eight transistor (8T) SRAM cell structure. The cells are designed with dual chirality and analyzed through simulation at two different temperatures (25°C and 110°C). A 6T CNFET based SRAM with dual chirality presented in reference literature is taken as reference for benchmarking the performance of the proposed cells. The proposed cells are effective in reducing the leakage power by more than 35% at 25°C and more than 60% at 110°C during standby mode of operation. Write leakage and average write power are also minimized at the expense of minimal increase (less than 5%) in write delay.
Microelectronics Journal 01/2013;
• ##### Article: Functions classification approach to generate reconfigurable fine-grain logic based on Ambipolar Independent Double Gate FET (Am-IDGFET)
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ABSTRACT: Am-IDGFET is a new family of particular devices in view of the fact that it associates three benefits: (i) it is usually a 1-D electronic device (CNT or SiNW), meaning high mobility, achievable current density and high ION/IOFF ratio; (ii) Independently controlled gates which offers the device extra logic options; (iii) ambipolar behaviour opens the way for N- and P-type polarities in the same device via its back gate. The creativity of this work consists of looking at this new class of emerging technology as an opportunity for new design paradigms with no equivalent counterparts in CMOS technology. Nevertheless, to build a feasible and complete picture of ambipolar logic, innovative design approaches and tools are required. In this paper, we exploit functional classification, a powerful tool for the construction and analysis of Boolean functions, to build reconfigurable logic blocks by defining a hierarchical correlation between structures of functions classes with ambipolar devices. We demonstrate how this approach enables us to build Am-I DGFET-based n-input reconfigurable cells. Several dynamically reconfigurable 2-inputs logic cells with partial and full functionality are designed in this paper. We evaluate the performances of circuits designed from this approach in a case study focused on Double Gate Carbon Nanotube FET (DG-CNTFET) technology. Simulations results show efficiency to build fine grain reconfigurable cells with partial functionality. In the case of 9-functions reconfigurable cell, an improvement of 1.8X in terms of power delay product (PDP) is proved when compared to a CMOS-16 nm technology. Fewer control signals are required and the area is reduced by 35% over CMOS technology.
Microelectronics Journal 01/2013;
• ##### Article: First integration of MOSFET band-to-band-tunneling current in BSIM4
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ABSTRACT: Static leakage currents represent a major issue in nano-scale CMOS. In digital VLSI circuits, the most relevant contributions to the overall leakage current are subthreshold conduction, gate current and band-to-band-tunneling (BTBT) current, which flows from drain/source to bulk through the reverse biased diffusion junctions. While the latter has been recognized as an important effect in digital nano-CMOS, yet no compact model of it has ever been included in the industry-standard device model BSIM4. In this work, we show that the lack of a BTBT current model leads to discrepancies between SPICE and device-level simulations and that adding a BTBT current source into BSIM4 DC model can correct this. The new current source follows a widely accepted physical model of the BTBT phenomenon with a rectangular junction approximation. Test case results show a good agreement between the new circuit-level simulations and the device-level extracted currents.
Microelectronics Journal 01/2013;
• ##### Article: Design of a three-stage ring-type voltage-controlled oscillator with a wide tuning range by controlling the current level in an embedded delay cell
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ABSTRACT: This paper presents a new design for a three-stage voltage-controlled differential ring oscillator embedded with a delay cell for a wide tuning range from 59 MHz to 2.96 GHz by adjusting the current level in the delay cell. The ring oscillator consists of a voltage-to-current converter, coder circuit, three-stage ring with delay cells, and current monitoring circuit to extend the tuning range of the proposed voltage-controlled oscillator. Each functional block has been designed for a minimum power consumption using the TSMC 0.18 μm CMOS technology. We simulate the performances of the proposed voltage-controlled oscillator in terms of phase noise, power consumption, tuning range, and gain. Our simulation results show that the proposed oscillator has the linear frequency–voltage characteristics over a wide tuning range. At each tuning range (mode), the calculated phase noise of the proposed ring oscillator at each tuning range (mode) was −87, −85, −81, and −79 dBc/Hz at a 1 MHz offset from the center frequency. The DC power of the proposed voltage-controlled oscillator consumed 0.86–3 mW under a 1.8 V supply voltage.
Microelectronics Journal 01/2013;
• ##### Article: Improved memristor-based relaxation oscillator
Microelectronics Journal 01/2013;
• ##### Article: A 33 mW 12.5 Gbps BiCMOS transmitter for high speed backplane applications
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ABSTRACT: This paper describes a 12.5 Gbps voltage mode transmitter with a high speed signal conditioning capability. Using a linear equalizer that is followed by a power efficient output stage, the transmitter achieves pre-emphasis at very low power consumption. In measurements, the transmitter can reliably transmit a 12.5 Gbps PRBS7 signal through a lossy 14 in. FR4 stripline commonly used in backplanes. It achieves a peak to peak jitter of 24 ps, a differential eye opening amplitude of 120 mV, and a maximum common mode ripple of 40 mV. The proposed topology consumes 33 mW at-speed power which includes both the output stage and the linear equalizer. It also passes 8KV HBM ESD testing without compromising the high speed capability. The transmitter is fabricated in a 130 nm BiCMOS technology with 100 GHz maximum ft and packaged in a commercial leadless leadframe package.
Microelectronics Journal 01/2013;
• ##### Article: Design considerations of calibration DAC in self-calibrated SAR A/D converters
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ABSTRACT: A capacitive calibration digital-to-analog converter (CDAC) is commonly used to reduce the mismatch-induced linearity errors for successive approximation register (SAR) analog-to-digital converters (ADC) employing capacitor arrays. There are complicated design considerations in determining the number of bits, the unit capacitor value and even the parasitic capacitors of the CDAC, as these factors affect or are determined by the achievable ADC resolution, the main DAC's capacitance, and the main DAC unit capacitance value, etc. This paper is the first to present a systematic analysis on these relationships. The analysis is validated by behavioral and circuit simulation results.
Microelectronics Journal 01/2013;
• ##### Article: System-level impacts of persistent main memory using a search engine
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ABSTRACT: Computer memory systems traditionally use distinct technologies for different hierarchy levels, typically volatile, high speed, high cost/byte solid state memory for caches and main memory (SRAM and DRAM), and non-volatile, low speed, low cost/byte technologies (magnetic disks and flash) for secondary storage. Currently, non-volatile memory (NVM) technologies are emerging and may substantially change the landscape of memory systems. In this work we assess system-level latency and energy impacts of a computer with persistent main memory using PCRAM and Memristor, comparing the development and execution of a search engine application implementing both a traditional file-based approach and a memory persistence approach (Mnemosyne). Our observations show that using memory persistence on top of NVM main memory, instead of a file-based approach on top DRAM/Disk, produces less than half lines of code, is more than 4× faster to develop, consumes 33× less memory energy, and executes search tasks up to 33× faster.
Microelectronics Journal 01/2013;
• ##### Article: Extraction of scalable electrical model for a SOI JFET using BSIM3 model
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ABSTRACT: It is well known that junction field effect transistor (JFET) has excellent behaviors in terms of low frequency noise (flicker noise). For this reason, it is used for all applications where noise must be as lower as possible and very high input impedance is needed.A JFET has been designed and realized in a BCD SOI technology and fully characterized in terms of DC, AC and noise measurements.To achieve an accurate modeling of the experimental data for circuit simulations, an evaluation of Schichman and Hodges JFET models has been carried out. However, basic limitations have been detected because subthreshold current is not described and model parameters are too few to properly fit the experimental data both in linear and saturation regions. Therefore it has been decided to carry study on modeling starting from the BSIM3 model equations.
Microelectronics Journal 01/2013;
• ##### Article: Impact of statistical parameter set selection on the statistical compact model accuracy: BSIM4 and PSP case study
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ABSTRACT: Statistical compact modeling (SCM) is necessary for variability aware design at nanometer regime. An extensive study has been carried out to evaluate the impact of the statistical parameter set selection on the statistical accuracy of two widely used industry standard compact models: BSIM4 and PSP. Different statistical parameter generation strategies have been employed to examine the impact of different statistical parameter selection on both device and circuit simulation accuracy.
Microelectronics Journal 01/2013;

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