Proceedings of the Custom Integrated Circuits Conference

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ISSN 0886-5930

Publications in this journal

  • Conference Paper: Analog techniques I
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    ABSTRACT: This year's CICC features two analog technique sessions. This session includes two invited papers and three regular papers that showcase a collection of analog techniques that enables high-performance analog designs.
    Custom Integrated Circuits Conference (CICC), 2013 IEEE; 01/2013
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    ABSTRACT: This paper presents a digitally controlled arbitrary waveform generator whose output voltage range is 0 to 7.5V under a 1.2V supply voltage. The high output voltage generation is realized using only 65nm standard MOS transistors. It consists of a voltage increasing block and a voltage decreasing block to realize stable high voltage output. Experimental results show that our waveform generator can generate arbitrary waveform, and it directly drives a MEMS structure.
    IEEE Custom Integrated Circuits Conference (CICC); 09/2012
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    ABSTRACT: This tutorial session covers a range of leading edge test, measurement, and debug technologies on power droop, noise, and jitter.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: A subthreshold ECG processor in IBM 45 nm SOI CMOS is designed to operate at the minimum energy operating point (MEOP). Statistical error compensation (SEC) is employed to further reduce energy (Emin) at the MEOP. SEC is shown to reduce Emin by 28% compared to the conventional (error-free) case while maintaining acceptable beat-detection performance. SEC enables the supply voltage to be scaled to 15% below its critical value at MEOP, while compensating for a 58% pre-correction error rate pe. These results represent an improvement of 19× in beat-detection performance, and 600× in pe over conventional (error-free) systems. The prototype IC consumes 14.5 fJ/cycle/1k-gate and exhibits 4.7× better energy efficiency than the state-of-the-art while tolerating 16× more voltage variations.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: High-speed data converters have become an integral part of wide-band wireless, wireline and networking applications with ever increasing data rates. In such systems reducing the power consumption of the A/D converter while increasing its sampling rate and linearity has remained a challenge. This fact has motivated many research groups to investigate potential solutions, which some of these efforts are highlighted in the following papers.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: Standby power reduction is critical to battery life and volume reduction in mm-scale sensor nodes. Power gating is extensively adopted to reduce leakage, but the inserted sleep transistors can suffer from other leakage mechanisms, namely GIDL, which become dominant at battery voltages of 3 V or higher. This paper introduces the concept of reconfigurable sleep transistors, in which two different topologies are used in active versus sleep mode. In active mode, transistors are stacked as in traditional power gating schemes. In sleep mode, sleep transistors are reconfigured to reduce GIDL current, in addition to subthreshold leakage. Measurements on a 180nm CMOS test chip shows 12.6× standby leakage reduction at VDD=4.0 V and T=25°C. This improvement comes with acceptable area penalty due to additional small reconfiguration transistors and separate body contacts, and no impact on active mode operation.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: This paper introduces an on-chip controller without off-chip components to reduce controller size for use as a Zero-Order-Control converter (ZOC). DC offset error by adding sawtooth signal in ZOC is self-corrected using a new control scheme, so as to overcome weak point of ZOC. This controller is applicable to both buck and boost, but a boost converter is chosen for verification here. A 0.35μm BCD process is used for chip with controller area of 0.791mm2. An efficiency of 90% is obtained for an 8 V output from 3.7 V at 480mW with 926 KHz.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: This paper describes a background digital calibration technique based on bitwise correlation (BWC) to correct the capacitive digital-to-analog converter (DAC) mismatch error in successive-approximation-register (SAR) analog-to-digital converters (ADC's). Aided by a single-bit pseudorandom noise (PN) injected to the ADC input, the calibration engine extracts all bit weights simultaneously to facilitate a digital-domain correction. The analog overhead associated with this technique is negligible and the conversion speed is fully retained (in contrast to [1] in which the ADC throughput is halved). A prototype 12bit 50-MS/s SAR ADC fabricated in 90-nm CMOS measured a 66.5-dB peak SNDR and an 86.0-dB peak SFDR with calibration, while occupying 0.046 mm2 and dissipating 3.3 mW from a 1.2-V supply. The calibration logic is estimated to occupy 0.072 mm2 with a power consumption of 1.4 mW in the same process.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
  • Conference Paper: Data converter techniques
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    ABSTRACT: The papers in this session highlight innovative architectures and circuit techniques to improve performance and reduce power consumption of analog-to-digital converters (ADC's).
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: For high data rates, pseudo-random bit sequence (PRBS) patterns must be generated in parallel and then multiplexed. This paper introduces a design that reduces the number of XORs and DFFs to lower power dissipation and area. The maximum fan-out can be further constrained to improve gate delay and hence improve the output data rate. The procedure for applying the design to arbitrary PRBS lengths is provided and the design is suitable for standard-cell design flow. The design achieves 1.7-Gb/s data rate with 64-way multiplexing to support an output bandwidth of >;100 Gb/s. The design is implemented in an 65-nm technology using 0.007 mm2 area and dissipating 0.16 mW of power.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: Phase Change Memory (PCM) technology is a promising candidate for the future non-volatile memory applications. Scaling of PCM into the sub-10 nm regime has been demonstrated using novel applications of nanofabrication techniques. PCM devices using solution-processed GeTe nanoparticles of diameter range 1.8-3.4nm has been demonstrated. Highly scaled (
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: This paper presents an energy-harvesting system consisting of amorphous-silicon (a-Si) solar cells and thin-film-transistor (TFT) power circuits on plastic. Along with patterned planar inductors, the TFTs realize an LC-oscillator that provides power inversion of the DC solar-module output, enabling a low-cost sheet for inductively-coupled wireless charging of devices. Despite the low performance of the TFTs (ft=1.3MHz at a voltage of 15V), the oscillator can operate above 2MHz by incorporating the device parasitics into the resonant tank. This enables increased quality factor for the planar inductors, improving the power-transfer efficiency and the power delivered. With 3cm-radius single- and double-layer inductors, the system achieves 22.6% and 31% power-transfer efficiency (approaching the analytically-predicted bound), while the power delivered is 20mW and 22mW.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: While the present market for power amplifiers in wireless handsets is largely met by GaAs HBTs, CMOS technology can provide major advantages including high integration levels, scalability, and digital control. This paper reviews possible directions for future CMOS PA development including FET stacking, envelope tracking, digital predistortion, and new architectures based on digital control, that promise to add to the advantages of CMOS in LTE applications.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: A motion artifact reduction multi-channel bio-signal sensor is proposed for sleep monitoring system with the help of independent component analysis (ICA). To prevent signal saturation due to large motion artifacts, adaptive DC level control (ADLC) is adopted to adjust the DC level of the signal. The current-controlled level shifter (CCLS) is used in ADLC for the shifting voltage step as small as 3mV with low power consumption. The shifted voltages and the motion artifacts are recovered by the ICA. The ICA also detects only the channels suffered from motion artifact and enables ADLC circuit of those selected channels to reduce standby power dissipation. The proposed 4-channel sleep monitoring sensor is implemented in a 0.13μm CMOS process, and consumes only 46μW. With the proposed ADLC, 17.7 times larger motion artifact cannot saturate signal.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: This paper discusses pre- and post-silicon electrical validation requirements for highly integrated designs and highlights the need for large-scale modeling and simulation of analog components in the context of validation. Current fast SPICE tools and Analog-Mixed Signal simulation do not provide the speed and scalability necessary to perform full cluster or system-level verification of high-speed IO links or to perform a variability analysis of these circuits. This paper outlines a method to scale the simulation of these circuits with correct accounting of voltage and temperature fluctuations, within-die and die-to-die variations, and platform uncertainty, with little loss in accuracy. The results are illustrated on a self-biased PLL example and illustrate the tremendous speedup that can be achieved while maintaining a comparable accuracy to SPICE for the behaviors that are modeled.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: A 63.5dB, 2MHz bandwidth ΔΣ ADC using two ICOs pseudo-differentially as an integrator/quantizer and a combined front-end switched-capacitor V-I converter and feedback DAC in 0.18μm without performance-enhancing calibration is presented. A novel high-linearity, temperature-independent, and voltage-independent ring oscillator architecture provides a high resolution quantizer output, and a digital ΔΣ loop truncates this for a 17-level feedback DAC. The custom portion of the design consumes 6.08mW of analog power from a 1.8V supply and occupies 0.152mm2.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: This all-Invited session covers advanced technologies, including the first production tri-gate devices, ultra-thin SOI, reliability challenges for scaled CMOS, and SiC devices for power management.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: Reliability is one of the major concerns in designing integrated circuits in deep nanometer CMOS technologies. Problems related to transistor aging like BTI or soft breakdown cause time-dependent circuit performance degradation. Variability only makes these things more severe. This creates a need for innovative design techniques and tools that help designers coping with these reliability and variability problems. This invited overview paper gives a brief description of device aging models. It also presents tools for the efficient analysis and identification of reliability problems in analog circuits. Finally, it proposes solutions for the design of resilient, self-healing circuits.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: A 100Mb/s 1.37mW impulse-radio ultra-wideband (IR-UWB) receiver with Costas-loop based frequency and phase synchronization scheme is developed in 65nm CMOS. This is the first analog-domain plesiochronous solution for IR-UWB communication in DC-960MHz band without the necessity of traditional analog-to-digital converter (ADC) and digital baseband for signal processing, thereby the receiver achieves the lowest energy of 13.7pJ/bit in state-of-the-art plesiochronous IR-UWB communication.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: In order to reduce the impact of resonant supply noise on processor performance, a simple, fully-digital and scalable technique based on staggering the activation time of the cores sharing the same power domain in a multi-core multi-power domain processor is presented. Measurement data from a 65nm test chip shows an Fmax improvement as large as 20% in a 3-core configuration. This is one of the first approaches to utilize the architecture level behavior for mitigating resonant noise issues in a multi-core multi-power domain processor.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012