Proceedings of the Custom Integrated Circuits Conference

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  • ISSN
    0886-5930

Publications in this journal

  • Conference Paper: Analog techniques I
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    ABSTRACT: This year's CICC features two analog technique sessions. This session includes two invited papers and three regular papers that showcase a collection of analog techniques that enables high-performance analog designs.
    Custom Integrated Circuits Conference (CICC), 2013 IEEE; 01/2013
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    ABSTRACT: This paper presents a digitally controlled arbitrary waveform generator whose output voltage range is 0 to 7.5V under a 1.2V supply voltage. The high output voltage generation is realized using only 65nm standard MOS transistors. It consists of a voltage increasing block and a voltage decreasing block to realize stable high voltage output. Experimental results show that our waveform generator can generate arbitrary waveform, and it directly drives a MEMS structure.
    IEEE Custom Integrated Circuits Conference (CICC); 09/2012
  • Conference Paper: Advanced memory topics
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    ABSTRACT: This session covers latest advances and future trends on phase change memory, high-density embedded DRAM, mega-byte class SRAM, and memory based physical unclonable functions.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: This paper presents the design and implementation of a family of high-performance soft-edge flip-flops (SEF) used in AMD products with core modules code-named “Bulldozer.” We highlight the benefits of the SEF and introduce a new method for comparing flip-flop designs in the presence of clock jitter. We describe an area-efficient level-sensitive scan design (LSSD) implementation in conjunction with supporting clock-gating circuitry for stand-by power reduction. We compare different SEF topologies along with flip-flops from previous designs.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). Our implementation includes a compression-decoding scheme to reduce the external memory bandwidth for Gaussian Mixture Model (GMM) computation and multi-path Viterbi transition units. We optimize the internal SRAM size using the max-approximation GMM calculation and adjusting the number of look-ahead frames. The test chip, fabricated in 40 nm CMOS technology, occupies 1.77 mm × 2.18 mm containing 2.52 M transistors for logic and 4.29 Mbit on-chip memory. The measured results show that our implementation achieves 34.2% required frequency reduction (83.3 MHz) and reduces 48.5% power consumption (74.14 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 2.4× faster than real-time at 200 MHz and 1.1 V with power consumption of 168 mW.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: Dithering in bang-bang controlled CDRs poses conflicting requirements on the phase adjustment resolution as one tries to maximize the tracking bandwidth and minimize jitter. A novel phase interval detector that looks for a phase interval enclosing the desired lock point is shown to find the optimal phase that minimizes the timing error without dithering. A digitally-controlled, phase-interpolating DLL-based CDR fabricated in 65nm CMOS demonstrates that it can achieve low jitter of 41-mUIp-p with a coarse phase adjustment step of 0.11-UI, while dissipating only 8.4mW at 5Gbps. In addition, a digitally-controlled in-situ measurement circuit that can characterize the CDR's jitter tolerance is presented.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: We have developed a power-gating technique for a mobile processor in 28-nm HKMG technology. The proposed EM-tolerant 1.8V I/O NMOS power switch reduces the standby power to 1/641× and achieves 79% channel utilization without weakening EM immunity. The active leakage power of the dual CPU cores can be reduced by 45 mW in a single core operation mode with a rapid 1.4-μs wakeup time to full core operation. A mobile processor is designed and fabricated with proposed technique. Estimated standby power of the chip is 123 μW, resulting in one order of magnitude reduction compared to the conventional techniques. Measured leakage power shows a good agreement with the estimated one.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: High-speed wireline communication links are ubiquitous in electronic systems today. Continuous research is pushing speed, power efficiency, flexibility, and ease-of-use of interfaces. This session includes some to latest advances in the wireline domain.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: We demonstrate an image sensor which directly acquires images in a compressed format. The sensor uses diffractive optical structures integrated in the CMOS back-end layer stack to compute a low-order 2D spatial Gabor transform on visual scenes. As this computation occurs in the optical domain, the readout back-end uses the transform outputs to implement the subsequent image digitization and compression simultaneously. Implemented in a 180nm logic CMOS process, the image sensor uses a 384×384 array of complementary angle-sensitive pixel pairs, consumes 2mW at a frame rate of 15fps, and achieves a 10:1 compression ratio on test images.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: A unified media application processor (UMAP) with a low-power mixed-mode feature extraction engine (FEE) is presented for 2D/3D image analysis/synthesis applications on handheld devices. UMAP supports not only graphics and vision for augmented reality (AR) but also 3D reconstruction and 3D display for 3D-view AR based on heterogeneous many-core platform. A frame-level 3-stage pipelined architecture enables real-time (50fps in VGA) performance in 3D-view AR, while a mixed-mode FEE dynamically saves active power by reconfiguring operation modes between analog and digital processing. Especially for low power operation in media processing, four pairs of analog current contention logics (CCL) are implemented in FEE. The implemented CCL does not require digital-to-analog or analog-to-digital converters (DAC/ADC) in interfacing digital and analog domains. It includes a diode-connected sensing stabilizer which reduces minimum sensing current. Therefore, average power consumed in CCL is reduced by 44.9%. In the implemented UMAP, the proposed FEE replaces the parallel processing core cluster in the analog processing mode, as a result, 96.5% of cluster power and 99.1% of target detection time are saved. The dynamic mode transition between analog and digital processing based on run-time tracking of region-of-interest (ROI) reduces system energy dissipation by up to 84.2% compared to the state-of-the-art embedded media processors.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: This paper describes the design of the architecture and circuit blocks for backplane communication transceivers. A channel study investigates the major challenges in the design of high-speed reconfigurable transceivers. Architectural solutions resolving channel-induced signal distortions are proposed and their effectiveness on various channels is investigated. Subsequently, the paper describes the design of a 0.6-13.1Gb/s fully-adaptive backplane transceiver embedded in state-of-the-art low-leakage 28nm CMOS FPGAs. The receiver front-end utilizes a 3-stage CTLE, a 7-tap speculative DFE, and a 4-tap sliding DFE to remove the immediate post-cursor ISI up to 64 taps. The clocking network provides continuous operation range between 0.6-13.1Gb/s. The transceiver achieves BER
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: This session explores modeling & design techniques for statistical variability and aging/reliability at the circuit level, and at the device level. It has five presentations/papers.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: A highly linear oscillator is presented for wideband polar modulation. It has both varactor voltage tuning for frequency locking and temperature compensation as well as inductive current tuning for linear phase modulation. Implemented in 65nm CMOS, it achieved a gain variation less than ±2% over more than 32MHz range meeting WCDMA polar modulation requirement. At 3.8GHz and 3MHz offset, its phase noise is -136.5dBc/Hz with current consumption of 18mA from 2.1V supply.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: Stacking devices in CMOS power amplifiers (PAs) increases the achievable output voltage swing, thereby increasing the output power and efficiency, particularly at millimeter-wave frequencies. This work presents stacked CMOS PAs based on an improved Class-E design methodology, where device loss is explicitly accounted for in the analysis and design procedure. Design guidelines and fundamental limits on achievable performance are presented. Two fully-integrated 45GHz prototypes with 2 and 4 stacked devices have been fabricated in IBM's 45nm SOI CMOS technology. Measurement results yield a peak PAE of 34.6% for the 2-stacked PA with a saturated output power of 17.6 dBm, and a peak PAE of 19.4% for the 4-stacked PA with a saturated output power of 20.3 dBm. The former represents the highest PAE reported for CMOS mmWave PAs, and the latter represents the highest output power achieved from a CMOS mmWave PA. The paper also describes the modeling of active and passive devices for mmWave CMOS PAs for good model-hardware correlation.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: Technologies featuring fully depleted transistors are entering the mainstream for designs at the 28nm, 20nm, and 14nm nodes. Although these devices have been the playground of device engineers for more than a decade it is for the most part only recently that they have been introduced to circuit designers and logic chip integrators. The physical structure and many of the features - or lack thereof - of the transistors vis-à-vis conventional planar devices are different, opening some new doors and perhaps closing some old ones. In this paper we discuss both planar (variously called ETSOI/UTBB/FDSOI1) and three-dimensional (variously called FinFET or trigate or doublegate) fully depleted devices, comparing and contrasting them with one another and with classical devices, and in both bulk and SOI manifestations.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: This tutorial session covers a range of leading edge test, measurement, and debug technologies on power droop, noise, and jitter.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: While the present market for power amplifiers in wireless handsets is largely met by GaAs HBTs, CMOS technology can provide major advantages including high integration levels, scalability, and digital control. This paper reviews possible directions for future CMOS PA development including FET stacking, envelope tracking, digital predistortion, and new architectures based on digital control, that promise to add to the advantages of CMOS in LTE applications.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: For high data rates, pseudo-random bit sequence (PRBS) patterns must be generated in parallel and then multiplexed. This paper introduces a design that reduces the number of XORs and DFFs to lower power dissipation and area. The maximum fan-out can be further constrained to improve gate delay and hence improve the output data rate. The procedure for applying the design to arbitrary PRBS lengths is provided and the design is suitable for standard-cell design flow. The design achieves 1.7-Gb/s data rate with 64-way multiplexing to support an output bandwidth of >;100 Gb/s. The design is implemented in an 65-nm technology using 0.007 mm2 area and dissipating 0.16 mW of power.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: High-speed data converters have become an integral part of wide-band wireless, wireline and networking applications with ever increasing data rates. In such systems reducing the power consumption of the A/D converter while increasing its sampling rate and linearity has remained a challenge. This fact has motivated many research groups to investigate potential solutions, which some of these efforts are highlighted in the following papers.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: This paper presents an energy-harvesting system consisting of amorphous-silicon (a-Si) solar cells and thin-film-transistor (TFT) power circuits on plastic. Along with patterned planar inductors, the TFTs realize an LC-oscillator that provides power inversion of the DC solar-module output, enabling a low-cost sheet for inductively-coupled wireless charging of devices. Despite the low performance of the TFTs (ft=1.3MHz at a voltage of 15V), the oscillator can operate above 2MHz by incorporating the device parasitics into the resonant tank. This enables increased quality factor for the planar inductors, improving the power-transfer efficiency and the power delivered. With 3cm-radius single- and double-layer inductors, the system achieves 22.6% and 31% power-transfer efficiency (approaching the analytically-predicted bound), while the power delivered is 20mW and 22mW.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012

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