Canadian Journal of Electrical and Computer Engineering Impact Factor & Information

Publisher: Canadian Society for Electrical Engineering; Institute of Electrical and Electronics Engineers. Canadian Region, Institute of Electrical and Electronics Engineers

Journal description

The CJECE publishes material in both English and French under three main headings: (a) Technical papers of between 3,000 and 8,000 words concerned with original research in the field of electrical and computer engineering, current electrical and computer engineering practice, or the history of electrical and computer engineering relevant to the Canadian scene. (b) Short papers directed to brief descriptions of new technical achievements, comments on the contents of previously published papers, or items of general interest to Canadian electrical engineers. (c) Application articles related to novel realizations, or major system implementations.

Current impact factor: 0.23

Impact Factor Rankings

2015 Impact Factor Available summer 2016
2014 Impact Factor 0.227
2012 Impact Factor 0.333
2011 Impact Factor 0.241
2010 Impact Factor 0.184
2009 Impact Factor 0.302
2008 Impact Factor 0.389
2007 Impact Factor 0.151
2006 Impact Factor 0.357
2005 Impact Factor 0.135
2004 Impact Factor 0.264
2003 Impact Factor 0.179
2002 Impact Factor 0.229
2001 Impact Factor 0.128
2000 Impact Factor 0.06
1999 Impact Factor 0.062
1998 Impact Factor 0.023
1997 Impact Factor 0.023
1996 Impact Factor 0.17

Impact factor over time

Impact factor

Additional details

5-year impact 0.29
Cited half-life -
Immediacy index 0.05
Eigenfactor 0.00
Article influence 0.11
Website Canadian Journal of Electrical and Computer Engineering website
Other titles Canadian journal of electrical and computer engineering (Online), Revue canadienne de génie électrique et informatique
ISSN 0840-8688
OCLC 61242421
Material type Document, Periodical, Internet resource
Document type Internet Resource, Computer File, Journal / Magazine / Newspaper

Publisher details

Institute of Electrical and Electronics Engineers

  • Pre-print
    • Author can archive a pre-print version
  • Post-print
    • Author can archive a post-print version
  • Conditions
    • Author's pre-print on Author's personal website, employers website or publicly accessible server
    • Author's post-print on Author's server or Institutional server
    • Author's pre-print must be removed upon publication of final version and replaced with either full citation to IEEE work with a Digital Object Identifier or link to article abstract in IEEE Xplore or replaced with Authors post-print
    • Author's pre-print must be accompanied with set-phrase, once submitted to IEEE for publication ("This work has been submitted to the IEEE for possible publication. Copyright may be transferred without notice, after which this version may no longer be accessible")
    • Author's pre-print must be accompanied with set-phrase, when accepted by IEEE for publication ("(c) 20xx IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.")
    • IEEE must be informed as to the electronic address of the pre-print
    • If funding rules apply authors may post Author's post-print version in funder's designated repository
    • Author's Post-print - Publisher copyright and source must be acknowledged with citation (see above set statement)
    • Author's Post-print - Must link to publisher version with DOI
    • Publisher's version/PDF cannot be used
    • Publisher copyright and source must be acknowledged
  • Classification

Publications in this journal

  • Canadian Journal of Electrical and Computer Engineering 10/2016; 38(3):253-265. DOI:10.1109/CJECE.2015.2406873

  • Canadian Journal of Electrical and Computer Engineering 10/2016; 38(3):266-273. DOI:10.1109/CJECE.2015.2416200
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    ABSTRACT: This paper is concerned with power oscillation damping in standalone microgrids (MGs) using an integrated series compensator. Power oscillation is the result of dynamic interaction between generating units and/or loads in a power system, which results in increased losses, power quality degradation, and momentary overloading of the converters used in converter-based grid-connected microsources (MSs) in MGs. Designing an MS controller to mitigate these oscillations is not straightforward as other performance criteria may need to be compromised. The proposed structure employs a small series compensator to mitigate the oscillations. In this paper, the dependence of power/frequency variation is analytically shown. It is explained how by introduction of a series voltage, this dependence can be minimized. The derivation of the small-signal model used for eigenvalue analysis is briefly explained. To validate the modeling and show the performance and robustness of the proposed controller, time-domain simulations are used. Discussions on the size of the proposed compensator and also on using different control parameters are presented.
    Canadian Journal of Electrical and Computer Engineering 12/2015; 38(1):2-9. DOI:10.1109/CJECE.2014.2328627
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    ABSTRACT: Cognitive radio is a system to utilize spectrum holes efficiently as a solution of spectrum scarcity. The availability of channels for secondary users is determined in the spectrum sensing phase by energy detection. Energy levels of sampled primary user’s (PU’s) signal can be measured by wavelet transform with more accuracy compared with Fourier-based methods. Wavelet packet-based spectrum sensing measures the energy level at each subcarrier and sets the decision threshold. However, at the first step of energy detection for wideband spectrum sensing, high-rate analog-to-digital converter (ADC) sampling requires a large dynamic range and high-speed signal processors. In this paper, compressed sampling for PU’s signal acquisition is proposed to reduce the rate of sampling and solve the implementation complexity of ADC. The simulation results verify that this mechanism is promising to estimate the power spectrum density (PSD) of PU’s signals. The graphs prove low side-lobes of the detected PSD and acceptable probability of detection and false alarm due to the target values and certain compression ratio.
    Canadian Journal of Electrical and Computer Engineering 12/2015; 38(1):31-36. DOI:10.1109/CJECE.2014.2355916
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    ABSTRACT: The growth of the Internet and telecommunication technology has facilitated remote access. During the last decade, many secure dynamic identity (ID)-based remote user authentication schemes have been proposed for the multiserver environment using smart cards. Recently, Li et al. point that the Lee et al. scheme is vulnerable to forgery attack, server spoofing attack, improper authentication, and unfriendly and inefficient password change. To overcome these security weaknesses, Li et al. propose a novel smart-card-and dynamic ID-based remote user authentication scheme for multiserver environments. In this paper, we show that the Li et al. scheme is also vulnerable to offline password guessing attack, stolen smart-card attack, forgery attack, and poor reparability. Their scheme does not also provide twofactor security. To provide a secure remote user authentication scheme for the multiserver environment and to overcome the security weaknesses, we propose an enhanced scheme. Our scheme is aimed at logically securing the data stored in the smart card and improving the dynamic property of the ID using password randomization for each session. Our scheme resists forgery attack, replay attack, stolen smart-card attack, offline password guessing attack, and spoofing attack. Our scheme's efficiency has been established analytically and confirmed through simulation.
    Canadian Journal of Electrical and Computer Engineering 12/2015; 38(1):20-30. DOI:10.1109/CJECE.2014.2344447
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    ABSTRACT: A novel line pilot differential protection principle based on the virtual impedance of fault component is proposed in this paper. First, according to the fault component of the measured current and voltage at both line ends, the fault component of the current and voltage at the line midpoint is calculated. Second, the virtual impedance is defined as the calculated voltage fault component divided by the calculated current fault component. And then, according to the two virtual impedances calculated at two line ends, the ratio restraint criterion is formed with the sum of the virtual impedances and the smaller virtual impedance. Finally, by analyzing different characteristics of the criterion in different fault cases, the fault can be identified. Simulation results verify that the proposed method is able to identify different kinds of fault accurately with high sensitivity. It is highly reliable and not affected by the fault location, transition resistance, load current, distributed capacitance, and data synchronization. Even in the case of transitional fault, selectivity can still be guaranteed with the proposed method.
    Canadian Journal of Electrical and Computer Engineering 12/2015; 38(1):37-44. DOI:10.1109/CJECE.2014.2356201
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    ABSTRACT: Commutation failure is a serious malfunction in high-voltage direct current (HVdc) converters and is mainly caused by ac side faults, where the change of dc current during fault conditions should be given adequate attention. Employing superconducting fault current limiters (SFCLs) for an HVdc system can suppress its dc fault current’s amplitude and maintain a small rate of the dc current change, which is helpful to inhibit the commutation voltage reduction. Accordingly, introducing SFCLs may act as one possible solution to decreasing HVdc commutation failure. In this paper, a flux-coupling-type SFCL is adopted to play this role. The SFCL’s topology structure and working principle are presented first, and then its influence mechanism to HVdc commutation failure is systematically investigated. Further, considering several different fault conditions, the transient performance of a 500-kV HVdc system equipped with the SFCLs is evaluated in MATLAB. From the results, installing the SFCLs can effectively decrease the duration of the commutation failure and facilitate the fault recovery process, and sometimes a possible successive commutation failure is avoided, as a result of improving the power transmission characteristics. Finally, in view of ac loss and equipment selection, the application feasibility of the SFCL for a high-voltage/large-scale system is preliminarily discussed, and some valuable conclusions are obtained.
    Canadian Journal of Electrical and Computer Engineering 12/2015; 38(1):10-19. DOI:10.1109/CJECE.2014.2335195
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    ABSTRACT: The growing demand for plug-in electric vehicles (PEVs) in the world has driven researchers to pay extra attention to charging stations (CSs) in order to meet supplying needs. Lower emission, convenient charging experience, high performance, and energy security are considered as the significant benefits of the mentioned technology. Despite the aforementioned advantages, inappropriate place and size of CSs have brought new challenges for electric distribution systems. Prominent features of distributed generations (DGs) make this technology appropriate for compensating relevant problems of CSs installation. In this paper, simultaneous optimal planning (placing and sizing) of CSs and DGs is presented to address new challenges. In addition, financial (investment costs), technical (system reliability, power loss, and voltage profile), and environmental (CO2 emission) issues are considered in the proposed objective function. A genetic algorithm is used to solve the optimization problem. Furthermore, the simulation study is carried out on a 33-bus radial distribution network. The simulation results show the effects of installation of CSs in the presence/absence of DGs on total costs, reliability, loss, voltage profile, and emission. Moreover, the effects of increasing PEV's availability are evaluated on the aforementioned terms in the electric distribution network.
    Canadian Journal of Electrical and Computer Engineering 09/2015; 38(3):238 - 245.

  • Canadian Journal of Electrical and Computer Engineering 08/2015;
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    ABSTRACT: Flash-memory-based solid-state drives use multiple NAND flash memory chips as storage media and deploy a large-sized random access memory (RAM) inside it. This RAM buffer absorbs the read and write requests by file systems, and thus the resulting write requests to NAND flash memory are determined by the buffer replacement scheme. Many of the previously proposed algorithms concentrate on improving the random write performance by reordering the writes, addressing the temporal locality, or evicting the clean pages beforehand. However, the sequential write patterns in the incoming write stream are not completely utilized by the flash translation layer; this increases garbage collection overhead. To overcome this limitation, we propose a novel algorithm, called random first flash enlargement (RFFE), to improve the performance of the write operation. The algorithm identifies the interleaved sequential writes and builds various policy decisions, and the write sequence is constructed by contemplating the flash memory characteristics. In particular, the write stream is written into an appropriate log block area. Trace driven simulation is compared with the previously proposed least recently used fully-associative sector translation (FAST), block padding least recently used (BPLRU), and recently-evicted-first (REF) buffer management schemes. The result shows that the RFFE outperforms the previously proposed schemes with respect to merge, erase, and write count.
    Canadian Journal of Electrical and Computer Engineering 06/2015; 38(3):219-231. DOI:10.1109/CJECE.2015.2431745
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    ABSTRACT: Power amplifiers (PAs) at millimeter-wave (mm-wave) frequencies are required for delivering high output linear power while being efficient; however, their performance is severely affected by the scaled semiconductor technology and the operating frequency. To improve the linearity of mm-wave PAs, it is recommended that an external linearization technique such as predistortion be used. The PA presented in this paper uses adaptive predistortion (APD). The APD linearization technique was developed using the Volterra series analysis on the silicon-germanium (SiGe) heterojunction bipolar transistor. The Volterra series analysis was used to identify and characterize the third-order intermodulation distortion components. The PA uses a single-ended common-emitter topology. It consists of three stages biased in the Class AB mode. The PA and APD were designed using the 130-nm SiGe bipolar and complementary metal-oxide-semiconductor process. The PA and APD achieve an optimum third-order intermodulation reduction of 10 dB and an improved linear output power of 2.5 dBm.
    Canadian Journal of Electrical and Computer Engineering 06/2015; 38(3):232-237. DOI:10.1109/CJECE.2015.2434941
  • X. Cui · M. Teng · J. Hu ·
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    ABSTRACT: It has been a challenge to determine the optimal energy-storage capacitance in piezoelectric vibration energy harvesting (VEH) systems for a given working time. In this paper, the PSPICE software is used to determine the optimal energy-storage capacitance in a VEH system with one or more piezoelectric modules, for maximizing the energy harvesting capability, and to investigate the dependence of this optimum energy-storage capacitance on the device and working parameters. The simulation method is verified by experimental results. It is found that the optimal energy-storage capacitance increases with an increase of the clamped capacitance, working frequency, and working time of the piezoelectric modules. It is also found that the optimal energy-storage capacitance is proportional to the number of the piezoelectric modules used in the VEH system if the piezoelectric modules have close parameters.
    Canadian Journal of Electrical and Computer Engineering 06/2015; 38(3):246-250. DOI:10.1109/CJECE.2015.2431312
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    ABSTRACT: To address the growing demand for high-quality multimedia applications on mobile devices, stronger smartphones based on multicore processors are becoming the mainstream. However, processing power is still behind the required resources for some multimedia applications such as new video coding standards. Mobile cloud computing is a solution for this concern. In order to efficiently distribute tasks onto an infrastructure of devices, a mapping algorithm is required. This algorithm should determine the suitable device in the cloud and should also allocate the corresponding core in the selected multicore device. Providing a suitable algorithm considering the two domains of cloud and Multiprocessor System on Chip (MPSoC) simultaneously is a challenge. Describing the mapping algorithms with a set of descriptive elements makes differentiation among them easier. Unification of these features on both domains results in simpler mapping algorithms. In this paper, we present a generic representation for the mapping algorithms in the MPSoC and cloud environments. Grounded Theory has been applied to identify the main features of the mapping algorithms. The obtained features are organized in more abstract categories based on their similarities. In order to evaluate the results, a few sample mapping algorithms from each of the cloud and MPSoC domains have been successfully characterized with the obtained features.
    Canadian Journal of Electrical and Computer Engineering 06/2015; 38(3):204-218. DOI:10.1109/CJECE.2015.2431220
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    ABSTRACT: Wireless networks use relay nodes as cooperative nodes to gain maximum diversity. Relay selection is one of the key challenging problems in multiuser wireless cooperative networks. This paper addresses the selection problem of the relay node and proposes posterior probability-based relay node selection methods. In these methods, all calculations are derived by either source or destination, consider both amplify–forward and decode–forward methods, and apply Bayesian decision theory to select the relay node. In the source-based method, each source node considers all the relay nodes’ channel information to estimate posterior probability using Bayes theorem, whereas in the destination-based method, the destination node considers all source node channel information to calculate posterior probability. Numerical results show that our proposed relay assignment methods maximize the overall data rate of the networks and work well independently of the number of relay nodes or source–destination pairs in the network.
    Canadian Journal of Electrical and Computer Engineering 05/2015; 38(2):116-124. DOI:10.1109/CJECE.2014.2386698
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    ABSTRACT: In this paper, we study the performance of long-term evolution (LTE) for various types of channel-adapted scheduling for nonreal-time flows, while an end-to-end congestion control algorithm controls the rate of elastic traffic at the end users. First, we propose a new type of queue-aware channel-adapted scheduling at a base station, and explain how it allocates resources to competing nonreal-time flows where channel conditions are time-varying. We also introduce a new congestion measure function for a minimum cost flow control (MCFC) algorithm in the LTE and call it an individual flow-based congestion measure. We show that using different combinations of channel-adapted scheduling at the base station and congestion control algorithms can lead to major differences in the obtained throughput and fairness for the best-effort traffic. The results clearly show that the transport protocol and scheduling algorithm can cause significant conflict in some situations. We show the advantages of the proposed queue-aware channel-adapted scheduling in performance improvement and we also show that the combination of an MCFC algorithm (in which the new individual flow-based congestion measure is applied), with queue-aware proportional fair scheduling, leads to a better tradeoff between overall throughput and fairness compared with the other studied combinations.
    Canadian Journal of Electrical and Computer Engineering 03/2015; 38(2):170-182. DOI:10.1109/CJECE.2015.2417858