Canadian Journal of Electrical and Computer Engineering (CAN J ELECT COMPUT E )

Publisher: Canadian Society for Electrical Engineering; Institute of Electrical and Electronics Engineers. Canadian Region, Institute of Electrical and Electronics Engineers

Description

The CJECE publishes material in both English and French under three main headings: (a) Technical papers of between 3,000 and 8,000 words concerned with original research in the field of electrical and computer engineering, current electrical and computer engineering practice, or the history of electrical and computer engineering relevant to the Canadian scene. (b) Short papers directed to brief descriptions of new technical achievements, comments on the contents of previously published papers, or items of general interest to Canadian electrical engineers. (c) Application articles related to novel realizations, or major system implementations.

  • Impact factor
    0.33
    Hide impact factor history
     
    Impact factor
  • 5-year impact
    0.42
  • Cited half-life
    0.00
  • Immediacy index
    0.20
  • Eigenfactor
    0.00
  • Article influence
    0.20
  • Website
    Canadian Journal of Electrical and Computer Engineering website
  • Other titles
    Canadian journal of electrical and computer engineering (Online), Revue canadienne de génie électrique et informatique
  • ISSN
    0840-8688
  • OCLC
    61242421
  • Material type
    Document, Periodical, Internet resource
  • Document type
    Internet Resource, Computer File, Journal / Magazine / Newspaper

Publisher details

Institute of Electrical and Electronics Engineers

  • Pre-print
    • Author can archive a pre-print version
  • Post-print
    • Author can archive a post-print version
  • Conditions
    • Author's pre-print on Author's personal website, employers website or publicly accessible server
    • Author's post-print on Author's server or Institutional server
    • Author's pre-print must be removed upon publication of final version and replaced with either full citation to IEEE work with a Digital Object Identifier or link to article abstract in IEEE Xplore or replaced with Authors post-print
    • Author's pre-print must be accompanied with set-phrase, once submitted to IEEE for publication ("This work has been submitted to the IEEE for possible publication. Copyright may be transferred without notice, after which this version may no longer be accessible")
    • Author's pre-print must be accompanied with set-phrase, when accepted by IEEE for publication ("(c) 20xx IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.")
    • IEEE must be informed as to the electronic address of the pre-print
    • If funding rules apply authors may post Author's post-print version in funder's designated repository
    • Author's Post-print - Publisher copyright and source must be acknowledged with citation (see above set statement)
    • Author's Post-print - Must link to publisher version with DOI
    • Publisher's version/PDF cannot be used
    • Publisher copyright and source must be acknowledged
  • Classification
    ​ green

Publications in this journal

  • [Show abstract] [Hide abstract]
    ABSTRACT: The objective of the software product line engineering paradigm is to enhance the largescale reuse of common core assets within a target domain. Reuse is facilitated by systematically organizing and modeling the core assets and the relationships between them. One of the main core assets of a domain is the model for representing the available functional aspects, often known as features, within structured forms such as feature models. The selection and composition of the most suitable or desirable set of features for a given purpose allows the rapid development of new final products from the software product line. Product developers are, in most cases, not only interested in building applications that possess certain functional characteristics but are also concerned with nonfunctional properties of the final product, such as reliability. To this end, we propose a componentbased software product line reliability estimation model that is able to provide lower and upper reliability bounds guarantees for a software product line feature model, its specializations and configurations. Our model builds on top of the reliability of the individual features that are present in the product line and provides best- and worst-case estimates. Our work is based on an essential and widely used assumption that features are implemented using self-contained software components or services whose reliability can be determined independently. We also propose reliability-aware configuration methods that ensure the satisfaction of both functional and reliability requirements during the application development process. We offer our observations and insight into the performance of our reliability estimation model and provide analysis of its advantages and shortcomings.
    Canadian Journal of Electrical and Computer Engineering 01/2014; 37(2):94-112.
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    ABSTRACT: The copy-on-write update policy is a powerful technique for data protection. Unfortunately, it introduces a recursive update problem, which causes several side effects to a storage system, such as WRITE amplification and performance degradation. This paper elaborates on how these effects are introduced by recursive update and how serious they are. In order to evaluate these effects, an extended BTRFS (the Linux B-tree Filesystem) prototype was developed to implement the update-in-place update policy for comparison. This paper reports that recursive update can lead to (29.5times ) WRITE amplification and 71% performance degradation in a single WRITE operation, as well as (18.3times ) WRITE amplification and 33% performance degradation in an e-mail server workload. These results indicate that taking recursive update into consideration is important in developing high performance and reliable file and storage systems.
    Canadian Journal of Electrical and Computer Engineering 01/2014; 37(2):113-122.
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    ABSTRACT: In this paper, static synchronous compensator (STATCOM)-based damping stabilizers are designed and implemented to enhance the damping of the low frequency oscillations. The effectiveness of STATCOM gain and phase modulation channels to improve the damping characteristics is investigated. The coordination among the internal ac and dc voltage controllers and the proposed damping controllers on each channel is designed. Differential evolution as an intelligent optimization technique is considered to design the STATCOM supplementary damping controllers. The STATCOM-based stabilizer is implemented on a real-time digital simulator (RTDS). The RTDS experimental setup of STATCOM with a power system is verified. The nonlinear time domain simulation of the considered power system is presented to validate the proposed damping stabilizers of low frequency oscillations. Comparisons with the reported results in the literature demonstrate the effectiveness of the proposed stabilizer.
    Canadian Journal of Electrical and Computer Engineering 01/2014; 37(1):48-56.
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    ABSTRACT: Hardware transactional memory (HTM) offers a promising parallel programming model for chip multiprocessors. The performance aspect of HTMs has been explored extensively, whereas little research has addressed the power of HTMs. In this paper, we investigate power consumption in HTMs and propose two optimization techniques. The first optimization technique is adaptive snoop granularity (ASG). HTMs rely on cache coherence protocols to detect conflicts and maintain consistency of transactional data. One of the main design issues facing HTMs is the growing number of snoops required to maintain coherency of transactional data. We found that many transactions access consecutive memory locations which are not shared by other transactions. ASG monitors these transactional accesses and dynamically changes snoop granularity to reduce the power of the interconnection network and eliminate needless cache snoops. The second optimization technique is transactional snoop filtering (TSF). TSF dynamically tracks accesses to the coherence caches and eliminates cache snoops that would result in cache misses. TSF relies on small filters to monitor cache addresses. Energy is reduced as accesses to the much more demanding data caches are decreased. We extended the Gem5 simulator to model ASG and TSF. Our simulation results show that ASG and TSF are effective and reduce energy of interconnects and caches up to 44% and 89%, respectively.
    Canadian Journal of Electrical and Computer Engineering 01/2014; 37(2):76-85.
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    ABSTRACT: In this paper, a new method for impulsive noise reduction and edge preservation in images is presented. Images of different characteristics corrupted with a wide range of impulsive noise densities using two impulsive noise models are examined using the proposed method. In the detection stage of the method, two conditions have to be met to determine whether an image pixel is noisy or not. Two predetermined threshold values are involved in the computation of the second condition to differentiate between corrupted and uncorrupted pixels. Only pixels determined to be noisy in the detection stage are filtered in the next filtering stage where small size sliding windows are used to significantly reduce blurring effects in the output restored images. Several measuring indices have been used to examine the performance of the proposed method compared with many existing state-of-the-art methods in the literature of the image restoration field. Extensive simulation results show the superior performance of the proposed method over other techniques in terms of restoration quality, and preservation of images with fine details and edges.
    Canadian Journal of Electrical and Computer Engineering 01/2014; 37(1):2-10.
  • [Show abstract] [Hide abstract]
    ABSTRACT: A new method to model the end effect for single-sided short-primary linear induction motors (LIMs) is developed by considering the effect of nonzero leakage inductance of the secondary. The well-established equivalent circuit model—introduced by Duncan in the 1980s—is improved by taking nonzero leakage inductance into account. This new approach closes the gap between predictions and test results of a transit LIM. It also allows for reliable model utilization in engineering practice. The analytical predictions are verified with the field test data collected from a full-scale LIM designed for public transit systems.
    Canadian Journal of Electrical and Computer Engineering 01/2014; 37(1):34-41.
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a state-of-the-art review of axial-flux permanent-magnet (AFPM) machines in the aspects of construction, features, electromagnetic and thermal modeling, simulation, analysis, design, materials, and manufacturing. Some key references on the above-mentioned aspects pertaining to the machine are discussed briefly. Particular emphasis is given on the design and performance analysis of AFPM machines. A comparison among different permanent magnet machines is also provided. Thus, this paper makes a bridge between the currently used permanent magnet machines in industry and the recent developments of AFPM machines.
    Canadian Journal of Electrical and Computer Engineering 01/2014; 37(1):19-33.
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    ABSTRACT: In this paper, a novel high-throughput very large scale integrated circuit architecture for a real-time implementation of intensity modulation direct detection optical orthogonal frequency division multiplexing system is proposed, achieving the highest throughput reported to date. The proposed architecture utilizes a fast, pipelined, and parallel inverse fast Fourier transform/fast Fourier transform in the transmitter/receiver, which is customized to satisfy the throughput requirements of the advanced optical systems. In addition, an efficient high-accuracy equalization method is developed, improving the system performance compared with the conventional linear equalizers. To evaluate the system performance, the OptiSystem software is used to model the optical channel and a Virtex-6 ML-605 evaluation board is used as the implementation platform. Moreover, the synthesis results in a 180-nm CMOS technology prove that the proposed architecture achieves a sustained throughput of 22.5 Gb/s with a 4.89- ({{rm mm}^{2}}) core area.
    Canadian Journal of Electrical and Computer Engineering 01/2014; 37(2):86-93.
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    ABSTRACT: This paper obtained the switching impulse flashover characteristic of live working complex gap on extra high voltage (EHV) and ultra high voltage (UHV) high-voltage transmission lines by a large number of experiments. Based on the experimental data and the leader inception discharge model, the complex gap discharge development during the process of entering equipotential and its influencing factors have been analyzed with the electric filed calculation method. Moreover, considering the practical conditions in live working sites, a complex gap discharge model appropriate for side live working on EHV and UHV high-voltage transmission lines has been proposed by introducing a revision coefficient $k_{m}$ . It has been found that $k_{m}$ is related to the working position and the structure of high-voltage electrode. Through further research on the establishment of the functional relationship, it can provide a comparable accurate theoretical calculation method for the research on the complex gap of live working and can give a guideline for optimizing the test plans.
    Canadian Journal of Electrical and Computer Engineering 01/2014; 37(1):11-18.
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    ABSTRACT: This paper develops an algorithm to estimate the space shift, time shift (or time delay), and parameters in a shifted continuous 2-D system described by a 2-D partial differential equation. Using the linear filter method, the simultaneous estimation of shifts and parameters is achieved. Also, the instrumental variable technique is used to remove the least square estimation bias, which is due to measurement noise. There are some methods to estimate the time shift in 1-D systems. However, no method has been proposed so far to estimate the shifts in 2-D systems. To show the performance of the proposed algorithm, one illustrative numerical example is discussed.
    Canadian Journal of Electrical and Computer Engineering 01/2014; 37(1):42-47.
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    ABSTRACT: The one-step predictive dead-time control circuit proposed in this paper consists of a dead-time detection circuit and an analog optimization circuit. The detection circuit, which can be manufactured on the same die as the synchronous MOSFET of the buck converter, provides an accurate detection signal that indicates body diode conduction. The proposed dead-time optimization circuit is an analog circuit, which uses the body diode detection signal and eliminates the shortcomings of digital dead-time detection circuits. Operation of the circuit is verified using PSIM. The results of the simulation show that the circuit reduces the body diode conduction time of the synchronous MOSFET to less than 4 ns at 20-A load, 12-V input, 1.2-V output, and 500-kHz switching frequency. As a result, the buck converter conduction losses can be reduced by 16.3%.
    Canadian Journal of Electrical and Computer Engineering 01/2013; 36(4):181-187.
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    ABSTRACT: This paper describes the design of an ultra-low-power analog front-end circuitry for a UHF passive RFID transponder. The design includes a voltage multiplier, a voltage regulator, a demodulator, a power-on-reset, a ring oscillator, a matching network and a backscatter modulator. We present a novel charge-pump circuit for improved voltage gain and power efficiency of RFID tags. The charge pump is fully integrable and takes advantage of both passive and active multiplication to reduce the required input power. The minimum required input power is ¿20.45dBm to generate a 1.2V supply voltage from a 50Ω antenna at 2.4GHz. The voltage multiplier efficiency is 15.95% for a 1MΩ load. The regulator consumes 602nW of DC power and maintains the range of the reference voltage variation to 0.1% while Vdd is varied from 0.8V to 2V. The PSNR of the regulator is -42dB at 2.45GHz frequency and remains greater than -32dB from 100Hz to 10GHz frequencies. The pulse width demodulator is used to extract the input data. The ring oscillator produces a 395 kHz clock for the digital section. Post-layout simulations show the overall power consumption is 1.8μW. The circuit is designed using the low-threshold 0.13μm Atmel CMOS technology. The operating distance of this RFID is in excess of 9 meters based on the regulated 4W EIRP in the US.
    Canadian Journal of Electrical and Computer Engineering 01/2013; 36(3):93-101.
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    ABSTRACT: Future wireless systems face challenges in supporting high-rate multimedia streaming with wide coverage area and at low power. Cooperative relaying is investigated in the following context: a single base station with multiple antennas simultaneously transmits different data streams to single-antenna destinations through a set of single-antenna fixed relays, with no direct link transmission between base stations and destinations. Transmission is via space-division multiple access with per-user quality-of-service constraints. The base station performs transmit beamforming (precoding) and relays cooperatively perform distributed beamforming. To address minimum-power source precoding and relay beamforming, the source precoder design with a fixed relay beamformer is first considered. Precoding is also generalized to multiple cooperating base stations. Next, the relay beamformer is optimized for a given source precoder and the process is iterated. The formulation is generalized to account for CSI estimates obtained from pilot symbol training. Simulation results quantify tradeoffs, including numbers of base station antennas and relays, effect of CSI quality on performance, as well as the impact of cooperating base stations.
    Canadian Journal of Electrical and Computer Engineering 01/2013; 36(2):68-77.
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    ABSTRACT: In this paper, the different singularity characteristics of differential current of transformer differential protection under inner-zone and out-zone faults are analyzed while the current transformer is saturated. Then, using grille fractal, a new approach to prevent maloperation of transformer differential protection is proposed. Combining the proposed approach with an adaptive generalized morphological filter, the singularity characteristic of the signal can be fully reserved. Meanwhile, noises and interferences can be restrained. It is not necessary for the proposed approach to accurately determine the moment when fault occurs and differential current appears. Using relative magnitude of smooth domain of maximal value and that of minimal value and by means of setting an appropriate threshold, the inner fault of the transformer can be reliably identified and the identification is not affected by inrush current. Besides, the evolved fault can be reliably identified. Results of dynamic simulation prove that the proposed approach is effective and feasible.
    Canadian Journal of Electrical and Computer Engineering 01/2013; 36(4):152-157.
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    ABSTRACT: Design of leading-one detector (LOD) and leading-one position detector (LOPD) are important as they are used for the normalization process in floating-point multiplication, floating-point addition/subtraction and in logarithmic converters. In this paper, the authors propose various gate-level architectures for LOD and LOPD. The LOD and LOPD circuits are evolved using the evolutionary algorithm (EA) and using the evolved lower-order gate structures, various higher-order circuits are constructed. To obtain better results, the EA is modified and a novel shuffling operation is performed to prevent the algorithm from settling in the local minima. Then the constructed LOD and LOPD circuit is synthesized using Cadence® RTLCompiler® using TSMC 180nm library. The LOD and LOPD circuits can be implemented in an Application Specific Integrated circuit (ASIC) or in a Field Programmable Gate Array (FPGA), and hence it is independent of the technology library. Perhaps the evolution can also be made as an intrinsic process during the application run time and the evolved best gate structure can be chosen. We restrict this paper to the extrinsic evolution of LOD and LOPD gate level architectures.
    Canadian Journal of Electrical and Computer Engineering 01/2013; 36(3):103-110.