Journal of Circuits System and Computers (J CIRCUIT SYST COMP)

Publisher: World Scientific Publishing

Journal description

Journal of Circuits, Systems and Computers is published six times a year, and covers a wide scope, ranging from mathematical foundations to practical engineering design in the general areas of circuits, systems, and computers. Although primary emphasis will be on research papers, survey, expository and tutorial papers are also welcome.

Current impact factor: 0.33

Impact Factor Rankings

2015 Impact Factor Available summer 2015
2013 / 2014 Impact Factor 0.33
2012 Impact Factor 0.238
2011 Impact Factor 0.281
2010 Impact Factor 0.215
2009 Impact Factor 0.264
2008 Impact Factor 0.099
2007 Impact Factor 0.13
2006 Impact Factor 0.116
2005 Impact Factor 0.248
2004 Impact Factor 0.264
2003 Impact Factor 0.047
2002 Impact Factor 0.158
2001 Impact Factor 0.091
2000 Impact Factor 0.444
1999 Impact Factor 0.289
1998 Impact Factor 0.105
1997 Impact Factor 0.06
1996 Impact Factor 0.101

Impact factor over time

Impact factor

Additional details

5-year impact 0.23
Cited half-life 7.00
Immediacy index 0.01
Eigenfactor 0.00
Article influence 0.06
Website Journal of Circuits, Systems, and Computers website
ISSN 0218-1266
OCLC 24310702
Material type Periodical, Internet resource
Document type Journal / Magazine / Newspaper, Internet Resource

Publisher details

World Scientific Publishing

  • Pre-print
    • Author can archive a pre-print version
  • Post-print
    • Author cannot archive a post-print version
  • Restrictions
    • 12 months embargo
  • Conditions
    • Author's pre-print on any website or open access repository
    • Author's post-print on author's personal website, institutional repository, subject repository or funding agency designated repository
    • Publisher's version/PDF cannot be used
    • Set statement to accompany pre-print and authors post-print - see policy
    • Must link to publisher version with DOI
  • Classification
    ​ yellow

Publications in this journal

  • Journal of Circuits System and Computers 07/2015; DOI:10.1142/S0218126615501303
  • Journal of Circuits System and Computers 07/2015; DOI:10.1142/S0218126615501418
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    ABSTRACT: Present study deals with the development of an artificial neural network (ANN)-based technique for tea quality quantification by monitoring fermentation and drying condition of the tea processing stages. An RS485 network-based instrumentation system has been developed and implemented for data collection for these two stages. Three calibrated sensor nodes are installed in the fermentation room due to its larger floor area to collect temperature and relative humidity (RH). Dryer inlet temperature is recorded using a calibrated thermocouple-based sensor node. From seven input parameters and target quality data obtained from tea taster, the ANN model has been developed to find the correlation between the process condition and the tea quality. From the correlation study, more than 90% classification rate is obtained from the model. The model is also validated with some independent data showing more than 60% correlation. Error in terms of root mean square error (RMSE) is about 0.17. This model will be helpful for improvement of tea quality.
    Journal of Circuits System and Computers 07/2015; DOI:10.1142/S021812661550139X
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    ABSTRACT: This work presents a bandgap voltage reference (BGR) integrated in 0.25-μm bipolar-CMOS-DMOS (BCD) technology. The BGR circuit generates a reference voltage of 1.22 V. It is able to withstand large supply voltage variations of vehicle applications from 4.5 V, e.g., in case of cranking, up to 60-V, maximum value in case of emerging 48-V battery systems for hybrid and electrical vehicles. The circuit has an embedded high-voltage (HV) pseudo-regulator block that provides a more stable internal supply rail for a cascaded low-voltage bandgap core. HV MOS are used only in the pre-regulator block thus allowing the design of a BGR with compact size. The proposed architecture permits to withstand large input voltage variations with a temperature drift of a hundred of ppm/°C, a line regulation (LR) of few mV/V versus the external supply voltage and a power supply rejection ratio (PSRR) higher than 90 dB.
    Journal of Circuits System and Computers 07/2015; DOI:10.1142/S021812661550125X
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    ABSTRACT: A mode-selectable oscillator (OSC) with variable duty cycle for improved charge pump efficiency is proposed in this paper. The novel OSC adjusts its duty cycle according to the operation mode of the charge pump, thus improves the charge-pump efficiency and dynamic performance. The control of variable duty cycle is implemented in digital logic hence it provides robust noise immunity and instantaneous response. The OSC and the charge-pump have been implemented in a 0.6-μm 40-V CMOS process. Experimental results show that the peak efficiency is 92.7% at 200-mA load, the recovery time is less than 25 μs and load transient is 15 mV under 500-mA load variation. The system is able to work under a wide range of input voltage (VIN) in all modes with low EMI.
    Journal of Circuits System and Computers 07/2015; DOI:10.1142/S0218126615501327
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    ABSTRACT: Because ternary computer has more superiority than other d-ary number systems, we focus on the investigation of ternary elementary quantum gates and the synthesis algorithm of ternary quantum logic circuits. Above all, Pauli operators and their matrices on qutrit are introduced. Then eight qutrit operators are selected as elementary operators and eight qutrit quantum logic gates are defined. Permutation groups are introduced to characterize the quantum gates and quantum logic circuits. Some important qutrit quantum logic gates are defined also, such as QNOT, QKCXi, EQKCXi, QSwap, QCNOT and EQCNOT. Based on these elementary gates, we prove two very important theorems: (1) all qutrit quantum reversible logic circuit can be generated by Xi gate and QKCXi gate; (2) all qutrit quantum reversible logic circuits can be generated by Xi gate and QCNOT gate. The two theorems indicate that any complicated qutrit quantum reversible circuit can be constructed by the simplest ternary quantum gate. This will greatly simplify the implementation difficulty of quantum circuit. Subsequently, we propose a synthesis algorithm for qutrit quantum reversible logic circuit, which is verified through simulation experiment by the computer program we have designed.
    Journal of Circuits System and Computers 07/2015; DOI:10.1142/S0218126615501212
  • Journal of Circuits System and Computers 07/2015; DOI:10.1142/S0218126615501157
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    ABSTRACT: This paper presents a technique towards obtaining an estimate of the value of inductor(s) to expand the bandwidth of operation in a complementary metal-oxide semiconductor (CMOS) amplifier system which exploits shunt peaking principle. The basic principle is placement of the zeros of the transfer function in an interleaved manner relative to the uncompensated RC time-constant frequency (TCF) and the band-edge frequency (BEF) (i.e., product of the poles) of the transfer function. Application of the analytical results has been demonstrated for (i) a common-gate (CG) amplifier stage in a 0.18-μm CMOS process and (ii) an inter-stage inductor coupling network which serves as an interface between two amplifier stages. MATLAB simulation has been used to obtain the range of design inductance values. The TSMC 180-nm CMOS process has been used in Cadence CAD environment to validate the theoretical predictions. The inductors laid out have been modeled using the ASITIC program to obtain more realistic results. The proposed technique provides a bandwidth extension of the CMOS common-gate amplifier from 6.68 GHz to 10.4 GHz with 1 dB peaking using only a 1.85-nH inductor. For the inter-stage coupling network, the suggested design procedure leads to a bandwidth extension ratio (BWER) exceeding three, with less than 3-dB ripple.
    Journal of Circuits System and Computers 07/2015; DOI:10.1142/S0218126615501194
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    ABSTRACT: This paper proposes a hybrid recurrent neuro-fuzzy (RNF) architecture for rotor speed regulation of indirect field oriented controlled (IFOC) induction motor (IM) drive. This approach incorporates Takagi–Sugeno–Kang (TSK) model-based fuzzy logic (FL) laws with a four-layer artificial neural networks (ANNs) scheme. Moreover, for the proposed RNF an improved self-tuning method is developed based on the IM theory and its high performance requirements. The principal task of the tuning method is to adjust the parameters of the FL in order to minimize the square of the error between actual and reference output. The convergence/divergence of the weights is discussed and investigated by simulation.
    Journal of Circuits System and Computers 07/2015; DOI:10.1142/S0218126615501315
  • Journal of Circuits System and Computers 07/2015; DOI:10.1142/S0218126615501248
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    ABSTRACT: Elliptic curve cryptosystems (ECC) are becoming more and more popular and are included in many standards, as they offer high security strength when compared with other conventional public-key cryptosystems, for the same key length. But the security strength of hardware implementations of ECC is challenged by side channel attacks (SCA) such as power analysis. Reversible logic circuits ideally consume zero energy, which serves as the motivation to implement cryptographic algorithms against power analysis attacks. This paper proposes two new hardware architectures for performing montgomery multiplication in GF(p) and GF(2m), as they are the power consuming operations in ECC. The two architectures are optimized to reduce the hardware cost and they are then implemented in reversible logic with reduced number of quantum cost. In this work, the reversible logic synthesis is performed with Toffoli family of reversible gates. The performance metrics of all the multipliers are analyzed and properly tabulated. Scalar multiplication on elliptic curve points, which is the core operation used in every elliptic curve cryptosystem, has been implemented in reversible logic by using the proposed reversible montgomery multipliers.
    Journal of Circuits System and Computers 07/2015; DOI:10.1142/S0218126615501224
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    ABSTRACT: A routing aggregation (RA) is proposed for load balancing network-on-chip (NoC). The computing nodes with dense traffic and long distance in network are gathered into the same routing node to form a super router. A load balancing routing algorithm for super router is presented to improve the overall performance of NoC. A simulation platform using System C is presented to confirm the feasibility of the proposed design in 2D mesh. The simulation results show that the proposed RA design can reduce the average packet latency and the standard deviation of host link utilization 8% and 33%, respectively compared with the reported routing methods. The area cost and power consumption compared with the reported schemes are 22% and 12% less, respectively.
    Journal of Circuits System and Computers 07/2015; DOI:10.1142/S0218126615501376
  • Journal of Circuits System and Computers 06/2015; DOI:10.1142/S0218126615501285
  • Journal of Circuits System and Computers 06/2015; DOI:10.1142/S0218126615501261
  • Journal of Circuits System and Computers 06/2015; DOI:10.1142/S0218126615501182
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    ABSTRACT: Microstrip Wilkinson power dividers with harmonic suppression and size reduction are investigated. It is found that by loading reactive components at the middle of high impedance transmission lines (TLs), both size reduction and harmonic suppression can be achieved. Analyses and designs of such a kind of power divider are formulated in this paper. To demonstrate the design methodology, two power dividers centered at 1.8 GHz are optimally designed and confirmed by experiments. As compared with conventional Wilkinson power divider, the proposed power divider exhibits 55.6% size reduction, and high suppressions are achieved for 2nd and 3rd harmonic components. Both simulations and measurements are presented with good agreement.
    Journal of Circuits System and Computers 06/2015; DOI:10.1142/S0218126615501273
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    ABSTRACT: Wide fan-in dynamic logic OR gate has always been an integral part of high speed microprocessors. However, low noise immunity of wide fan-in dynamic logic gate is always an issue of concern. For maintaining high noise immunity, various large sized PMOS keeper-based dynamic OR gates are proposed in the literature. These designs allow large leakage through them for maintaining high noise immunity which unnecessarily increases the power dissipation. This can be a critical issue for microprocessors used in battery operated devices. Independent gate (IG) FinFET devices are known to reduce leakage current through them using back gate biasing technique. In this paper, a novel FinFET-based wide fan-in dynamic OR gate has been proposed with effective leakage control and high noise immunity. This work reports a maximum leakage power reduction up to 70% while maintaining up to 90% higher noise immunity as compared to standard dynamic OR gate at low keeper size. This work also mathematically illustrates the effective leakage reduction capability of FinFET as compared to CMOS and hence proves its preference over CMOS in wide fan-in dynamic OR gate.
    Journal of Circuits System and Computers 06/2015; 24(05):1550073. DOI:10.1142/S0218126615500735