Journal of Circuits System and Computers (J CIRCUIT SYST COMP)

Publisher: World Scientific Publishing

Journal description

Journal of Circuits, Systems and Computers is published six times a year, and covers a wide scope, ranging from mathematical foundations to practical engineering design in the general areas of circuits, systems, and computers. Although primary emphasis will be on research papers, survey, expository and tutorial papers are also welcome.

Current impact factor: 0.33

Impact Factor Rankings

2015 Impact Factor Available summer 2015
2013 / 2014 Impact Factor 0.33
2012 Impact Factor 0.238
2011 Impact Factor 0.281
2010 Impact Factor 0.215
2009 Impact Factor 0.264
2008 Impact Factor 0.099
2007 Impact Factor 0.13
2006 Impact Factor 0.116
2005 Impact Factor 0.248
2004 Impact Factor 0.264
2003 Impact Factor 0.047
2002 Impact Factor 0.158
2001 Impact Factor 0.091
2000 Impact Factor 0.444
1999 Impact Factor 0.289
1998 Impact Factor 0.105
1997 Impact Factor 0.06
1996 Impact Factor 0.101

Impact factor over time

Impact factor

Additional details

5-year impact 0.23
Cited half-life 7.00
Immediacy index 0.01
Eigenfactor 0.00
Article influence 0.06
Website Journal of Circuits, Systems, and Computers website
ISSN 0218-1266
OCLC 24310702
Material type Periodical, Internet resource
Document type Journal / Magazine / Newspaper, Internet Resource

Publisher details

World Scientific Publishing

  • Pre-print
    • Author can archive a pre-print version
  • Post-print
    • Author cannot archive a post-print version
  • Restrictions
    • 12 months embargo
  • Conditions
    • Author's pre-print on any website or open access repository
    • Author's post-print on author's personal website, institutional repository, subject repository or funding agency designated repository
    • Publisher's version/PDF cannot be used
    • Set statement to accompany pre-print and authors post-print - see policy
    • Must link to publisher version with DOI
  • Classification
    ​ yellow

Publications in this journal

  • [Show abstract] [Hide abstract]
    ABSTRACT: Microstrip Wilkinson power dividers with harmonic suppression and size reduction are investigated. It is found that by loading reactive components at the middle of high impedance transmission lines (TLs), both size reduction and harmonic suppression can be achieved. Analyses and designs of such a kind of power divider are formulated in this paper. To demonstrate the design methodology, two power dividers centered at 1.8 GHz are optimally designed and confirmed by experiments. As compared with conventional Wilkinson power divider, the proposed power divider exhibits 55.6% size reduction, and high suppressions are achieved for 2nd and 3rd harmonic components. Both simulations and measurements are presented with good agreement.
    Journal of Circuits System and Computers 06/2015; DOI:10.1142/S0218126615501273
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    ABSTRACT: In the case of the reconfigurable module, the popular logic function implementation is based on the look-up-table (LUT) structure. Once a Boolean network of single-rail n-variable node functions is transformed into a dual-rail one, each variable is represented as two literals: x and its inversion x′ and implemented using two separate signals. As a result, (2n + 1)-input LUTs are required for mapping node functions. To reduce the capacity of required LUTs, the literal decomposition method is proposed. It is applied to implement a dual-rail node function using k-input LUTs, n < k < (2n + 1). The literal decomposition over the chosen variable is based on creating two clusters where one of the clusters contains minterms with the literal x of the chosen variable, the other one contains minterms with the literal x′. Functions created based on each cluster minterms depend on less literals number than the original one. The procedure is repeated until the required number of literals is reached. The literal decomposition is used as a post processing of the conventional decomposition procedure. Depending on the logic architecture, different implementations are considered and discussed. The implementation complexity (in terms of LUTs number) for different values n, k is given.
    Journal of Circuits System and Computers 06/2015; DOI:10.1142/S0218126615501108
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    ABSTRACT: Wide fan-in dynamic logic OR gate has always been an integral part of high speed microprocessors. However, low noise immunity of wide fan-in dynamic logic gate is always an issue of concern. For maintaining high noise immunity, various large sized PMOS keeper-based dynamic OR gates are proposed in the literature. These designs allow large leakage through them for maintaining high noise immunity which unnecessarily increases the power dissipation. This can be a critical issue for microprocessors used in battery operated devices. Independent gate (IG) FinFET devices are known to reduce leakage current through them using back gate biasing technique. In this paper, a novel FinFET-based wide fan-in dynamic OR gate has been proposed with effective leakage control and high noise immunity. This work reports a maximum leakage power reduction up to 70% while maintaining up to 90% higher noise immunity as compared to standard dynamic OR gate at low keeper size. This work also mathematically illustrates the effective leakage reduction capability of FinFET as compared to CMOS and hence proves its preference over CMOS in wide fan-in dynamic OR gate.
    Journal of Circuits System and Computers 06/2015; 24(05):1550073. DOI:10.1142/S0218126615500735
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    ABSTRACT: This paper proposed an adaptive neuro-fuzzy model (ANFIS) to multilevel inverter (MLI) for grid connected photovoltaic (PV) system. The purpose of the proposed controller is that it is not requiring any optimal pulse width modulated (PWM) switching-angle generator and proportional-integral controller. The proposed method strictly prohibits the variations present in the output voltage of the cascaded H-bridge MLI. In this method, the ANFIS have the input which is grid voltage, the difference voltage and the output target is control voltage. By using these parameters, the ANFIS makes the rules and has been tuned perfectly. During the testing time, the ANFIS gives the control voltage according to the different inputs. The resultant control voltage equivalent gate pulses are utilized for controlling the insulated gate bi-polar switches (IGBT) of MLI. Then the ANFIS based MLI for grid connected PV system is implemented in the MATLAB/simulink platform and the effectiveness of the proposed control technique is analyzed by comparing with the neural network (NN), fuzzy logic control, etc. The comparison results demonstrate the superiority of the proposed approach and confirm its potential to solve the problem. A prototype of three-phase grid connected cascaded H-bridge inverter has been developed using field-programmable gate array (FPGA) and results are analyzed.
    Journal of Circuits System and Computers 06/2015; 24(05):1550066. DOI:10.1142/S0218126615500668
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    ABSTRACT: In 2003, a digitally controlled oscillator (DCO) for cellular mobile phones was first proposed and demonstrated, and after that DCOs are widely used along with the rapid development of wireless communications. DCOs based on LC structure gain an advantage over ring oscillators in phase noise and thereby become research hotspot during the last decade. This paper presents a review of inductance capacitance (LC)-DCOs classified by circuit topologies and performance. For each DCO structure, the principle exposition and performance analysis are given in detail. Moreover, a comparison among all kinds of DCOs mentioned in this paper is presented in tabular form. Finally, we discuss the obstacle to the development of DCOs and the possible tendency for future work in summary.
    Journal of Circuits System and Computers 06/2015; 24(05):1530002. DOI:10.1142/S0218126615300020
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    ABSTRACT: It is important in digital signal processing (DSP) architectures to minimize the silicon area of the integrated circuits. This can be achieved by reducing the number of functional units such as adders and multipliers. In literature, folding technique is used to reduce the functional units by executing multiple algorithm operations on a single functional unit. Register minimization techniques are used to reduce the number of registers in a folded architecture. Retiming is a technique that needs to be performed before applying folding. In this paper, retiming is performed based on nature inspired evolutionary computation method. This technique generates the database of solutions from which best solution can be picked for folding further. As a part of this work, an efficient folded noise removal audio filter prototype is designed as an application example using evolutionary computation-based retiming and folding with register minimization. Folding technique will however increase the number of registers while multiplexing datapath adder and multiplier elements. Register minimization technique is used after folding to reduce the number of registers. After obtaining retimed, folded filter architecture, low level synthesis is performed which involves mapping of datapath adder and multiplier blocks to actual hardware. Various architectures of adders and multipliers are compared in area-power-performance space and depending on the user defined constraint, folded architecture with specific combination of data path elements is mapped on to hardware. A framework is designed in this paper to automate the entire process which reduces the design cycle time. All the designed filters are targeted for ASIC implementation. The results are compared and are provided as part of simulation results.
    Journal of Circuits System and Computers 06/2015; 24(05):1550068. DOI:10.1142/S0218126615500681
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    ABSTRACT: STRIKE is an algorithm which predicts protein-protein interactions (PPIs) and determines that proteins interact if they contain similar substrings of amino acids. Unlike other methods for PPI prediction, STRIKE is able to achieve reasonable improvement over the existing PPI prediction methods. Although its high accuracy as a PPI prediction method, STRIKE consumes a large execution time and hence it is considered to be a compute-intensive application. In this paper, we develop and implement a parallel STRIKE algorithm for high-performance computing (HPC) systems. Using a large-scale cluster, the execution time of the parallel implementation of this bioinformatics algorithm was reduced from about a week on a serial uniprocessor machine to about 16.5 h on 16 computing nodes, down to about 2 h on 128 parallel nodes. Communication overheads between nodes are thoroughly studied.
    Journal of Circuits System and Computers 06/2015; 24(05):1550074. DOI:10.1142/S0218126615500747
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    ABSTRACT: Tri-state boost power factor correction (PFC) converter operating in pseudo-continuous-conduction mode (PCCM) is analyzed in this paper. The connection of power switch in parallel with inductor makes the boost converter operate in PCCM, which provides an additional degree of control freedom by inductor current freewheeling operation mode. Compared with boost PFC converter operating in continuous conduction mode (CCM) and discontinuous conduction mode (DCM), tri-state boost PFC converter extends the load range and is therefore more suitable for wide range of load variation. However, for universal input applications, the input power factor (PF) of the tri-state boost PFC converter is relatively low when the sinusoidal reference current control strategy is used. To improve the PF over the whole input voltage range, the input current and PF expressions of the tri-state boost PFC converter is derived and the non-sinusoidal reference current control strategy is proposed. A 400 W prototype of the tri-state boost PFC converter is built by using digital signal processing (DSP) as the controller. The experimental results verify the analysis results.
    Journal of Circuits System and Computers 06/2015; 24(05):1550072. DOI:10.1142/S0218126615500723
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    ABSTRACT: Primary-side regulated (PSR) flyback controller has been widely used in low power charger applications for its simple structure, low cost, good electrical isolation and compact volume. However, limited by traditional primary-side sensing technology, PSR flyback controller suffers from poor dynamic response. A low standby power PSR flyback controller with fast dynamic response has been presented, and novel feedback comparison and sampler combo controlling circuit has been presented in the paper. An offline PSR controller containing the proposed speedup circuit and driving directly power bipolar junction transistor (BJT) was fabricated in Episil 1.0 μm 40 V/5 V EPI-HVCMOS process. Measured result shows that, in the entire universal input-voltage range (90 Vac-264 Vac) and 5 V 1.0 A output power, the proposed PSR controller achieves standby power less than 22 mW and average efficiency line end with 20 AWG 1.5 m up to 78%. The output voltage of the proposed PSR controller becomes stable within 3.3 ms when load current changes abruptly from 0 to 1 A and from 1 A to 0.
    Journal of Circuits System and Computers 06/2015; 24(05):1550069. DOI:10.1142/S0218126615500693
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    ABSTRACT: This paper proposes a new blind approach for time synchronization of orthogonal frequency division multiplexing (OFDM) receivers (RX). It is largely known that the OFDM technique has been successfully applied to a wide variety of digital communications systems over the past several years — IEEE 802.16 WiMax, 3GPP-LTE, IEEE 802.22, DVB T/H, ISDB-T, to name a few. We focus on the synchronization for the ISDB-T digital television system, currently adopted by several South American countries. The proposed approach uses the coarse synchronization to estimate the initial time reference and then, the fine synchronization keeps tracking the transmitter (TX) time reference. The innovation on the proposed approach regards to the closed loop control stabilization of the fine synchronization. It uses a smith predictor and a differential estimator, which estimates the difference between TX and RX clock frequencies. The proposed method allows the RX to track the TX time reference with high precision ( sample fraction). Thus, the carriers phase rotation issue due to incorrect time reference is minimized, and it does not affect the proper RX IQ symbols demodulation process. The RX internal time reference is adjusted based on pilot symbols, called scattered pilots (SPs) in the context of the ISDB-T standard, which are inserted in the frequency domain at the inverse fast Fourier transform (IFFT) input in the TX. The averaged progressive phase rotation of the received SPs at the fast Fourier transform (FFT) output is used to compute the time misalignment. This misalignment is used to adjust the RX fine time synchronism. Furthermore, the proposed method has been implemented in an ISDB-T RX. The FPGA-based receiver has been evaluated over several multipath, Doppler and AWGN channel models.
    Journal of Circuits System and Computers 06/2015; 24(05):1550076. DOI:10.1142/S0218126615500760
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    ABSTRACT: In this paper, a new highly linear operational transconductance amplifier (OTA) is presented. Proposed OTA employs two linearization techniques of cross-coupled double differential pairs and resistive source degeneration to achieve highly linear response under low power consumption. Considering the linearity and the frequency response issues as main parameters of OTA in the communication circuits, design procedure is theoretically formulated for the best linearity and optimum frequency compensation. Proposed OTA is simulated in 0.18-μm TSMC CMOS technology by Hspice simulator. While, the power consumption is only 467 μW, applying two-tone input voltage with amplitude of 0.6 Vp-p at 10 MHz frequency results in -61 dB third-order intermodulation (IM3) distortion of the output current that still remains below -44 dB for amplitudes up to 1 Vp-p. A precise frequency response analysis is performed which has resulted in optimum values of resistor and capacitor for miller compensation. Using common mode feedback in both stages and push-pull based output stage lead to 108 dB CMRR at DC that decreases to 84.5 dB at 100 kHz frequency.
    Journal of Circuits System and Computers 06/2015; 24(05):1550071. DOI:10.1142/S0218126615500711
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    ABSTRACT: This paper proposes a simultaneous multithreaded matrix processor (SMMP) to improve the performance of data-parallel applications by exploiting instruction-level parallelism (ILP) data-level parallelism (DLP) and thread-level parallelism (TLP). In SMMP, the well-known five-stage pipeline (baseline scalar processor) is extended to execute multi-scalar/vector/matrix instructions on unified parallel execution datapaths. SMMP can issue four scalar instructions from two threads each cycle or four vector/matrix operations from one thread, where the execution of vector/matrix instructions in threads is done in round-robin fashion. Moreover, this paper presents the implementation of our proposed SMMP using VHDL targeting FPGA Virtex-6. In addition, the performance of SMMP is evaluated on some kernels from the basic linear algebra subprograms (BLAS). Our results show that, the hardware complexity of SMMP is 5.68 times higher than the baseline scalar processor. However, speedups of 4.9, 6.09, 6.98, 8.2, 8.25, 8.72, 9.36, 11.84 and 21.57 are achieved on BLAS kernels of applying Givens rotation, scalar times vector plus another, vector addition, vector scaling, setting up Givens rotation, dot-product, matrix-vector multiplication, Euclidean length, and matrix-matrix multiplications, respectively. The average speedup over the baseline is 9.55 and the average speedup over complexity is 1.68. Comparing with Xilinx MicroBlaze, the complexity of SMMP is 6.36 times higher, however, its speedup ranges from 6.87 to 12.07 on vector/matrix kernels, which is 9.46 in average.
    Journal of Circuits System and Computers 05/2015; DOI:10.1142/S0218126615501145
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    ABSTRACT: A new single phase bridgeless power factor correction (PFC) converter derived from CUK topology is proposed. In this new CUK converter, the absence of the front end diode bridge results in the less switching and conduction losses compared to the conventional PFC converter. The current flow in the proposed converter configuration has only two semiconductor switches and it results in less conduction loss during each interval of the switching cycle. It offers less input current ripple, less electromagnetic interference (EMI) and also protection against the starting inrush current. It is mostly preferred compared to the other PFC topologies since it has both continuous input and output currents with a reduced current ripple. The proposed converter uses the simple control strategy and is made to work in the discontinuous conduction mode (DCM) to achieve almost a unity power factor. It also offers zero current turn ON and turn OFF for power switches. The performance of the proposed PFC converter is tested in MATLAB/SIMULINK environment with fuzzy logic controller (FLC). The simulation results of the proposed new CUK PFC converter validate the effectiveness of FLC in power factor enhancement.
    Journal of Circuits System and Computers 05/2015; DOI:10.1142/S0218126615501029
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    ABSTRACT: Spatial multiplexing of local elements (SMILE) is a front-end architecture which uses one radio frequency (RF) channel to carry multiplexed information from multiple ones. For this scheme, this paper proposes a fully multiplexing 0.35-μm RF CMOS integrated circuit (IC). The one uses an low noise amplifier (LNA) with four inputs to accomplish the multiplexing. To translate the frequency to the base-band, a double-balanced mixer and a voltage-controlled oscillator (VCO) are used. The presented results are satisfactory, validating the proposed compact design, and showing the viability of this topology for SMILE applications.
    Journal of Circuits System and Computers 05/2015; DOI:10.1142/S0218126615501078
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    ABSTRACT: The paper proposes hierarchical scheduling optimization scheme in hybrid cloud. Our proposed hierarchical scheduling takes advantage of the interaction of cloud users, private cloud and public cloud. For high level optimization in hybrid cloud, the objective of public cloud provider optimization is to maximize the revenue of providing virtual machines (VMs) and minimize the energy cost. The private cloud users' applications give the unique optimal payment to public cloud providers under deadline and cost constraint to maximize the satisfaction of private cloud user applications. The objective of low-level scheduling optimization is to minimize the cost and execution time of private cloud application. From the simulation results, the revenue, execution success ratio and resource utilization of our proposed hierarchical scheduling algorithm are better than other related works.
    Journal of Circuits System and Computers 05/2015; DOI:10.1142/S021812661550111X
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    ABSTRACT: A dual-modulus prescaler (divide-by-2/3) using complementary clocking NMOS-like blocks is presented in this paper. The prescaler can work properly for both differential and single phase input clocks. For differential input clocks, the prescaler achieves not only high operating frequency but also low power consumption since it consists of only five NMOS-like blocks. For single phase input clock, the operating frequency range is further expanded by utilizing a complementary clocks generator. Simulation results show that, in 180-nm standard CMOS technology, the proposed prescaler achieves operating frequency range of 1.7-9.0 GHz for differential input clocks and 0.5-10.2 GHz for single phase input clock. And the maximum power consumption from 1.8 V power supply is 0.92 mW and 1.32 mW for differential and single phase input clocks respectively.
    Journal of Circuits System and Computers 05/2015; DOI:10.1142/S0218126615501091
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    ABSTRACT: A novel gain-tunable output buffer for audio-DAC is proposed in this paper. With this proposed architecture, the common-mode output voltage can be independent of gain variation. In practical applications, supply voltage might change. With this proposed architecture, the common-mode output voltage could be set separately, to guarantee that it stays in the mid-scale position of the supply. Therefore, the ability of reaching the maximum output swing for the buffer features the proposed architecture. In addition, the threshold current reference is utilized to generate bias currents for the other building blocks. Therefore, it is always located in the source position of the signal chain. Its output noise would be amplified by all the following circuit blocks. To guarantee high-quality performance of the audio-DAC, the output noise of the threshold current reference should be suppressed. In this letter, noise performance of the threshold current reference is analyzed theoretically and improved significantly. Simulation result shows that the integrated noise current of the threshold current reference can be reduced from 0.61 to 0.15 nA when the integral frequency range sweeps from DC to 50 kHz, i.e., a reduction of 75.4% has been achieved.
    Journal of Circuits System and Computers 05/2015; DOI:10.1142/S0218126615501066