Journal of Circuits System and Computers (J CIRCUIT SYST COMP )

Publisher: World Scientific Publishing


Journal of Circuits, Systems and Computers is published six times a year, and covers a wide scope, ranging from mathematical foundations to practical engineering design in the general areas of circuits, systems, and computers. Although primary emphasis will be on research papers, survey, expository and tutorial papers are also welcome.

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  • Website
    Journal of Circuits, Systems, and Computers website
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  • Material type
    Periodical, Internet resource
  • Document type
    Journal / Magazine / Newspaper, Internet Resource

Publisher details

World Scientific Publishing

  • Pre-print
    • Author can archive a pre-print version
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    • Author cannot archive a post-print version
  • Restrictions
    • 12 months embargo
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    • Author's pre-print on any website or open access repository
    • Author's post-print on author's personal website, institutional repository, subject repository or funding agency designated repository
    • Publisher's version/PDF cannot be used
    • Set statement to accompany pre-print and authors post-print - see policy
    • Must link to publisher version with DOI
  • Classification
    ​ yellow

Publications in this journal

  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper introduces a method for detection and identification of IGBT-based drive open-circuit fault of DTC induction motor drives. The detection mechanism is based on soft set theory and wavelet decomposition, if it is detailed, ⊼-product decision making method and sym2 wavelet decomposition have been used in the detection mechanism. In this method, the stator currents have been used as an input to the system. The stator current has been used for the detection of the fault. The signal analysis has been performed up to the six level details wavelets decomposition. Faulty switch is detected by applying soft set theory to sixth level wavelets transformation. This is the first time applied to inverter in induction motor drives fault detection. The results demonstrate that the proposed fault detection and diagnosis system has very good capabilities.
    Journal of Circuits System and Computers 02/2015; 24(2):1-14.
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper proposes two high performance binary-to-binary coded decimal (BCD) conversion algorithms for use in BCD multiplication. These algorithms are based on splitting the 7-bit binary partial product of two BCD digits into two groups, computing the contribution of each group to the equivalent BCD partial product, and adding these contributions to compute the ¯nal BCD partial product. Designs for the proposed architectures and their implementations targeting both ASIC and FPGA are compared with others. Implementations of BCD array multipliers using both our conversion circuits and existing conversion circuits have been per- formed. The synthesis results for both ASIC and FPGA show that the proposed designs are faster and occupying less area than the state-of-the-art conversion circuits. Furthermore, the results obtained from comparing BCD multipliers of various sizes show that the enhancement in the area of the conversion circuit grows into a sizable area improvement in the multiplier circuit.
    Journal of Circuits System and Computers 02/2015; 24(2).
  • Journal of Circuits System and Computers 10/2014;
  • Journal of Circuits System and Computers 10/2014; 23(09):1450132.
  • Journal of Circuits System and Computers 10/2014;
  • [Show abstract] [Hide abstract]
    ABSTRACT: The memristor has drawn the worldwide attention since it has been discovered at HP laboratory on 1 May 2008. Since then many researchers are taking e®orts to ¯nd its applications in various areas. In this paper, we study the ¯lter characteristics of ¯rst-order low pass and high pass ¯lters employing memristor with a capacitor. The paper provides a comparative analysis between low pass and high pass ¯lter circuits that utilizing ordinary resistor or memristor with a capacitor. The theoretical analyzes are veri¯ed with SPICE simulation results using a memristor SPICE model with nonlinear dopant drift and MATLAB environment. The e®ect of change of the input frequency and initial resistance value of memristor on the cut-o® frequencies of the presented low pass and high pass ¯lters are investigated. The memory e®ect of memristor is represented by simulation results.
    Journal of Circuits System and Computers 09/2014; 23(8).
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    ABSTRACT: As networks-on-chips (NoCs) are expected to provide the necessary scalable communication medium for future many-core systems-on-chips (SoCs) optimizing their resources is of great importance. What is really needed is an efficient NoC architecture with optimized resources that requires very little customization by the SoC developers. One of the most important area and power hungry resources is the NoC's buffers. In this work, a new Modified Fat Tree (MFT) NoC architecture with buffers engineered for maximum efficiency (performance versus area) is presented. Extensive simulations are used to show optimum buffer design/placement under different conditions of traffic types and NoC sizes.
    Journal of Circuits System and Computers 06/2014; 23(07).
  • [Show abstract] [Hide abstract]
    ABSTRACT: To solve the problem that it is difficult to install isolation resistors across each output port, a new five-way microstrip Wilkinson power divider with double-layer topology is developed. The isolation resistors are placed on the second substrate by using half-wavelength microstrip transmission lines with the introduction of Archimedean spirals to reduce the circuit size. To demonstrate the design method, a five-way equal power divider is designed; its size is optimized at the center frequency of 2.45 GHz. The fabricated sample has been tested. Measured results are in good agreement with simulations.
    Journal of Circuits System and Computers 06/2014; 23(07).
  • [Show abstract] [Hide abstract]
    ABSTRACT: Localization and tracking technology based on received signal strength indicator (RSSI) is one of the most popular topics because of its low demand on hardware and cost. But the complexity of the indoor environment, leads to the uncertainty of the radio propagation which can seriously affect the positioning accuracy based on the received signal strength. Focused on the wall reflection in the indoor environment, the radio propagation characteristic based on ray-tracing model is analyzed and one strategy for the near wall localization is presented. The actual hardware platform and experimental test results show the applicability of the empirical logarithmic path loss model for localization and the effect of the wall reflection.
    Journal of Circuits System and Computers 06/2014; 23(07).
  • [Show abstract] [Hide abstract]
    ABSTRACT: Although parallel multipliers are optimal for speed, they occupy considerable chip area. For applications with lengthy operands as cryptography, the required area grows further. On the other hand, digit multipliers reduce chip area at the expense of the number of cycles required to complete the multiplication. In such multipliers, one-or-both inputs are received serially one digit per cycle. Digit multiplier designs are flexible with respect to the digit width enabling designers to select the most suitable compromise between area and cycle count for the application under consideration. This paper proposes a new digit serial–serial multiplier that is more area efficient compared to other functionally-similar multipliers. First, we propose a new unsigned digit serial–serial multiplier that is area efficient. The multiplier has the ability to handle unequal-width operands. That is, one operand can be of dynamic width (unlimited digit count) and the other operand is of fixed width. Moreover, with a small modification, the multiplier can operate on two's complement operands. Then, the design is extended to support bit-level pipelining: the critical path of the multiplier pipeline stage is independent of the operand width and the digit width. Simulation results show that the proposed multiplier reduces the area over similar multipliers by up to 28% and reduces power by up to 31%.
    Journal of Circuits System and Computers 06/2014; 23(07).
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    ABSTRACT: "Vedic mathematics" is the ancient methodology of mathematics which has a unique technique of calculations based on 16 "sutras" (formulae). A Vedic squarer design (ASIC) using such ancient mathematics is presented in this paper. By employing the Vedic mathematics, an (N × N) bit squarer implementation was transformed into just one small squarer (bit length ≪ N) and one adder which reduces the handling of the partial products significantly, owing to high speed operation. Propagation delay and dynamic power consumption of a squarer were minimized significantly through the reduction of partial products. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using 90-nm CMOS technology. The propagation delay of the proposed 64-bit squarer was ~ 16 ns and consumed ~ 6.79 mW power for a layout area of ~ 5.39 mm2. By combining Boolean logic with ancient Vedic mathematics, substantial amount of partial products were eliminated that resulted in ~ 12% speed improvement (propagation delay) and ~ 22% reduction in power compared with the mostly used Vedic multiplier (Nikhilam Navatascaramam Dasatah) architecture.
    Journal of Circuits System and Computers 06/2014; 23(07).
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this study, active and passive control techniques are applied for the synchronization of two identical Vilnius chaotic oscillators. The differential equations of Vilnius oscillator are described according to its circuit model. Based on Lyapunov function, the active and passive controllers are used to realize the synchronization of Vilnius chaotic systems. Numerical simulations are presented to verify and compare the effectiveness of proposed control techniques.
    Journal of Circuits System and Computers 06/2014; 23(07).
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a transadmittance-mode (TAM) universal biquad filter with independently electronic tunability. The proposed biquad filter only employs three operational transconductance amplifiers (OTAs) and two grounded capacitors which are the minimum components count necessary for realizing independently electronic tunability of the parameters ω0 and ω0/Q without the need of control factors matching conditions. Moreover, the proposed circuit still achieves nearly all of the main advantages: (i) simultaneous realizations of universal filtering responses (low-pass, high-pass, band-pass, band-reject and all-pass) from the same topology, (ii) versatile input/output functions, (iii) orthogonally electronic tunability of the parameters ω0 and Q without the need of control factors matching conditions, (iv) no need of any resistors, (v) cascadable feature for all input and output terminals, (vi) no need of extra inverting or non-inverting amplifiers, (vii) the employment of only grounded capacitors, (viii) no component-value constraints (except for allpass filter function) and (ix) low active and passive sensitivity performances. H-spice simulations with TSMC 0.35 μm 2P4M CMOS process technology validate theoretical predictions.
    Journal of Circuits System and Computers 06/2014; 23(07).