Proceedings of The International Symposium on Multiple-Valued Logic

Description

  • Impact factor
    0.00
  • 5-year impact
    0.00
  • Cited half-life
    0.00
  • Immediacy index
    0.00
  • Eigenfactor
    0.00
  • Article influence
    0.00
  • ISSN
    0195-623X

Publications in this journal

  • [Show abstract] [Hide abstract]
    ABSTRACT: The paper studies ternary logic functions that have decision diagrams of identical shape. The concept of beads, a special class of binary sequences, is extended to ternary sequences and are used to describe the shape of the decision diagrams representing functions that are mathematical models of such sequences. We point out that establishing the links between beads, functions, and their decision diagram representations can be useful in classification of ternary functions, checking the equivalence of functions, as well as their circuit implementations.
    43rd International Symposium on Mutiple-Valued Logic; 05/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: A linear algebraic method is developed that allows for logic network justification problems to be solved. The method differs from previous techniques that require learning or solution space search techniques in that all possible justification solutions are determined through a single vector-matrix product calculation. The logic network is represented by a matrix that is defined as the "justification" matrix. It is shown that the justification matrix is simply the transpose of the network transfer matrix and is thus easily obtained through a traversal of the network netlist. Example justification calculations are provided.
    Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on; 01/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: Ternary switching functions are formulated as transformations over vector spaces resulting in a characterization in the form of a transfer function. Ternary logic constants are modeled as vectors, thus the transfer functions are of the form of matrices that map vectors representing logic network input values to corresponding output vectors. Techniques for determination of the transfer matrix from a logic switching model or directly from a netlist are provided. The use of transfer matrices for logic network simulation are then developed that allow for multiple output responses to be obtained through a single vector-matrix product calculation.
    Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on; 01/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: A new basic switching gate based on differential logic is proposed for implementing high-performance low-voltage VLSI. Differential switching gate operates in current domain and output voltage swing can be determined independent of supply voltage, which leads to a high frequency operation even if in a lower-supply-voltage condition. Moreover, the use of a modified pMOS load further improves the transient characteristic of the switching gate. Through an evaluation of a differential logic-based combinational circuit, a potential capability of the differential switching gate is demonstrated.
    Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on; 01/2013
  • Conference Paper: Boolean Max-Co-Clones
    [Show abstract] [Hide abstract]
    ABSTRACT: In our ISMVL 2012 paper we introduced the notion of max-co-clone as a set of relations closed under a new type of quantification, max-quantification. This new concept was motivated by its connections to approximation complexity of counting constraint satisfaction problems. In this paper we go beyond scattered examples of max-co-clones and describe all max-co-clones on a 2-elements set (Boolean max-co-clones). It turns out that there are infinitely many Boolean max-co-clones and that all of them are regular co-clones, although it is not true for larger sets. Also there are many usual co-clones that are not closed under max-quantification, and therefore are not max-co-clones.
    Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on; 01/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: Shramko-Wansing's trilattice logics are sixteen-valued logics based on the algebraic structures of trilattices that can suitably represent generalized truth values. In this paper, an alternative new proof of the cut-elimination and completeness theorems for such a trilattice logic is obtained using two embedding theorems. Moreover, the Craig interpolation and Maksimova separation theorems for this logic are proved using the same embedding theorems. The results on Craig interpolation and Maksimova separation are new results of this paper.
    Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on; 01/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: Stochastic decoding provides ultra-low-complexity hardware for high-throughput parallel low-density parity-check (LDPC) decoders. Asynchronous stochastic decoding was pro- posed to demonstrate the possibility of low power dissipation and high throughput in stochastic decoders, but decoding might stop before convergence due to "lock-up", causing error floors. In this paper, we introduce wire-delay dependent asynchronous stochastic decoding to reduce the error floors. Instead of assigning the same delay to all computation nodes in the previous work, different computation delay is assigned to each computation node depending on its wire length. The variation of update timing increases switching activities to decrease the possibility of the "lock-up", lowering the error floors. BER performance using a regular (1024, 512) (3, 6) LDPC code is simulated based on our timing model that has computation and wire delays estimated under ASPLA 90nm CMOS technology. It is demonstrated that the proposed asynchronous decoder achieves an up to 0.25-dB gain compared with that of the synchronous and the conventional asynchronous decoders.
    IEEE 43rd International Symposium on Multiple-Valued Logic (ISMVL 2013), Toyama, Japan; 01/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: A noise-tolerant model of a ternary inverter is proposed based on extension of Markov Random Field (MRF). Simulation results are reported to justify the noise immunity of this model using PSPICE and 16-nm Berkeley CMOS technology.
    Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on; 01/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper surveys research activities in multiple-valued logic (MVL), and focuses on the International Symposium on Multiple-valued Logic (ISMVL). It spans 40 years. Using four different databases, lists of highly cited papers on MVL are shown, and research topics are analyzed.
    Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on; 01/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: Tactile graphics are useful for visually impaired students when they study mathematics and science. However, producing tactile graphics is not simple task. An intelligent computer-aided system for assisting the production of tactile graphics is needed. To develop such a system, research on mathematical graph recognition techniques is needed. This paper focuses on a method of mathematical graph recognition. When drawing a mathematical graph, we use not only solid lines, but also use broken lines. This paper describes a method for extracting and classifying broken line elements from mathematical graphs.
    Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on; 01/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: This research work focuses on join operations and some lattice structures in BCK-algebras. As the main result, the authors introduce a new definition of a join operation on commutative BCK-algebra with condition (S) instead of the boundedness property.
    Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on; 01/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: An 8-bit successive approximation analog-to-digital converter (SA ADC) has been designed and fabricated by using a 0.18-μm technology. A generalized non-binary algorithm has been used to enhance operation speed by relaxing the settling constraint of the DAC output. A split-capacitor array with a monotonic switching scheme has also been incorporated to reduce the power consumption. Transistor-level simulation shows an effective number of bits (ENOB) of 7.91 bits under a Nyquist condition with a sampling frequency of 2 MHz. Fabricated chip operates successfully, proving the design principle.
    Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on; 01/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: Reversible logic is an emerging research area that has shown promising results in applications such as quantum computing, low power design, and optical computing. Since the synthesis of minimal circuits is a cumbersome task, many synthesis algorithms apply heuristics and can therefore not provide a minimal solution. As a consequence, post synthesis methods such as window optimization and template matching are being applied. Template matching algorithms explore the circuits for gate cascades that can be replaced by smaller ones using a special class of identity circuits, so called templates. The determination of cascades applicable for substitution is the bottleneck of the template matching algorithm and problem-solving methods have been proposed in the recent past. Since these algorithms are based on heuristics, it cannot be ensured that a matching cascade can always be found. In this paper, we propose a new approach that determines matching cascades based on Boolean satisfiability and therefore ensures that these cascades are always found if they exist. Experimental results demonstrate that template matching yields smaller circuits when applying the new method for cascade determination.
    Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on; 01/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: Lifestyle diseases are strongly associated with lifestyle disease and the serious case of cardiovascular events which are main causes of long term nursing care. They would have strong impacts on the coming super aging society. In response to the problems to be solved, the notion technology of Systems Health Care and its technology have been proposed and developed by the authors to support health care in home and medical especially for lifestyle modification. In the framework, the important tools of Health Management Technology are investigated to be effective and efficient roles in the process of health management. The tools are Index, Criterion, and Causality which plays the roles in the health management functions of measurement, recognition, and estimation respectively. The applications are studied from the views of the tools; i.e., visceral fat and blood pressure are employed as the indices of vital signs and daily activities, sleep condition, and weight standing for diet as lifestyle habits.
    Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on; 01/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: This study presents an efficient cluster-based tribes optimization algorithm (CTOA) to design neuro-fuzzy systems (NFS) for chaotic time series prediction. The proposed CTOA learning algorithm was used to parameter optimization of the NFS model. The CTOA adopts a self-clustering algorithm (SCA) to divide suitably a swarm into multiple tribes and uses different displacement strategies let each particle to select to update. Furthermore, the CTOA also utilizes adaptation mechanism to generate or remove particles and reconstruct tribal links to make the tribes to more adaption and improve the qualities of the tribes to evolve. Finally, the proposed NFS-CTOA method is applied to predict chaotic time series. Results of this study demonstrate the effectiveness of the proposed CTOA learning algorithm.
    Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on; 01/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper describes practical applications on computational medical and health care technology. First, we briefly describe medical image processing for diagnosing. Next, we demonstrate three ultrasonic surgery support systems for orthopedic surgeon, rectum cancer surgeon and urologist. In them, image and signal processing plays a primary role to solve each problem. Second, we describe home health care system. This goal is not clinical use but home use to pay consciousness to health. In it, we introduce a mat senor system, which detects heart rate and respiration, and a thermopile senor system, which detects human moving trajectory. Finally, body weight prediction methods are shown by using autoregressive model. As the results, the models successfully predict the body weights.
    Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on; 01/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: The aim of this study is to present electrooculogram signals that can be used for human computer interface efficiently. Establishing an efficient alternative channel for communication without overt speech and hand movements is important to increase the quality of life for patients suffering from Amyotrophic Lateral Sclerosis or other illnesses that prevent correct limb and facial muscular responses. In this paper, we introduce the gaze estimation system of electrooculogram signals. Using this system, the electrooculogram signals can be recorded when the patients focused on each direct. All these recorded signals could be analyzed using math-method and the mathematical model will be set up. Gaze estimation can be recognized using electrooculogram signals follow these models.
    Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on; 01/2013

Related Journals