Proceedings of The International Symposium on Multiple-Valued Logic

Publications in this journal

• Conference Proceeding: The Tensor PMV-algebra of an MV-algebra

  I. Leustean
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  ABSTRACT: The classical construction of tensor algebra is done in the context of MV-algebras. We construct the tensor PMV-algebra of an MV-algebra, which yields an adjunction between the category of MV-algebras and the category of PMV-algebras. In particular, for any MV-algebra A, the tensor PMV-algebra of A is the free PMV-algebra over A.
  Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on; 06/2011
• Conference Proceeding: Determining Minimized Galois Field Expressions for Ternary Functions

  R.S. Stankovic, H. Astola, J.T. Astola
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  ABSTRACT: The paper extends the notion of the Special Normal Form (SNF) for Boolean functions to ternary logic functions. An algorithm to minimize the generalized Galois field (GF) expressions for ternary functions by using SNF is presented.
  Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on; 06/2011
• Source

  Available from: uni-rostock.de

  Conference Proceeding: Galois Theory for Partial Clones and Some Relational Clones

  K. Schölzel
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  ABSTRACT: A Galois connection between partial clones and a new variant of relation algebras is established. We introduce a new elementary operation on relations which captures the difference between total and partial clones and allows us to adapt the proof of the Galois connection from the total case to the partial case. This Galois connection is able to capture all partial clones and is not restricted to strong partial clones as in previous work.
  Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on; 06/2011
• Conference Proceeding: A Three-Valued Approach to the Master Argument

  S. Akama, Y. Nagata
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  ABSTRACT: The Master Argument due to Diodorus Cronos claims that nothing is possible that neither is true nor will be true and that therefore every (present) possibility must be realized at a present or future time. Unfortunately, it leads to logical determinism. In this paper, based on Prior's insight, a three-valued approach to the Master Argument is presented by developing a three-valued modal tense logic with a Kripke semantics. We also discuss philosophical and logical issues in connection with other approaches.
  Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on; 06/2011
• Conference Proceeding: Error-Correcting Decision Diagrams for Multiple-Valued Functions

  H. Astola, S. Stankovic, J.T. Astola
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  ABSTRACT: Decision diagrams are an efficient way of representing switching functions and they are easily mapped to technology. The layout of a circuit is directly determined by the shape of the decision diagram. By combining the theory of error-correcting codes with decision diagrams, it is possible to form robust circuit layouts, which can detect and correct errors. The method of constructing robust decision diagrams is analogous to the decoding process of linear codes, and can be based on simple matrix and look-up operations. In this paper, we focus on error-correcting decision diagrams for multiple-valued functions, considering them for both the Hamming metric and the Lee metric. The performance of robust decision diagrams is analyzed by determining the error probabilities for such constructions. Depending on the error-correcting properties of the code used in the construction, the error probability of a circuit can be significantly decreased by a robust decision diagram.
  Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on; 06/2011
• Conference Proceeding: Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme

  S. Matsunaga, A. Katsumata, M. Natsui, T. Hanyu
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  ABSTRACT: A novel compact and static-power-free nonvolatile ternary content-addressable memory (TCAM) cell, where two-bit nonvolatile magnetic tunnel junction (MTJ) devices are stacked over the comparison logic circuit, is proposed for a high-density and ultra low-energy fully-parallel TCAM. The use of nonvolatile logic-in-memory circuit architecture makes it possible to realize 6T-2MTJ TCAM cell structure. The 144-bit word match-line is divided into two parts (first 10-bit and last 134-bit parts), which greatly reduces the dynamic power dissipation with small overhead of the switching delay. In fact, it is evaluated by the HSPICE simulation under a 90nm CMOS/MTJ technology that the search energy (power-delay product) of the proposed TCAM is reduced to 16 percent in comparison with that of a nonvolatile TCAM without using a segmented match-line scheme.
  Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on; 06/2011
• Conference Proceeding: Information-Preserving Logic Based on Logical Reversibility to Reduce the Memory Data Transfer Bottleneck and Heat Dissipation

  M. Lukac, Ben Shuai, M. Kameyama, D.M. Miller
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  ABSTRACT: We present an approach to the cache bottleneck problem using reversible logic circuits. The high traffic between the cache and the main memory in current systems considerably slows down the performance of the general information processing unit (IPU). Moreover this high traffic has the consequence of high heat generation in VLSI elements such as the CPU or dedicated processors. Thus the reduction in use or complete removal of the cache memory could be beneficial to current processors architecture. We present a model where the IPU is designed as a logically reversible circuit. This allows one to reduce the cache memory traffic because data can be recovered using the output of the current processing. We illustrate the implementation of the approach by providing a design of an adiabatic reversible Toffoli gate with a power consumption equivalent to a classical adiabatic circuit. With these approaches, the cache-memory bottleneck and heat dissipation can potentially be reduced even by using only logically reversible circuit implementation.
  Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on; 06/2011
• Conference Proceeding: Comparison of Influence of Two Data-Encoding Methods for Grover Algorithm on Quantum Costs

  S. Dhawan, M. Perkowski
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  ABSTRACT: It is important to be able to calculate realistic estimates of quantum costs for real oracles used in quantum algorithms. In this paper, we compare Perkowski's oracle data encoding method with Hogg's encoding method for Grover algorithm, to examine the decrease in Oracle gate cost, if any, for four common constraint satisfaction problems: Graph coloring, Satisfiability, Send-More-Money and Max Clique.
  Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on; 06/2011
• Conference Proceeding: Synthesis of Reversible Synchronous Counters

  M.H.A. Khan, M. Perkowski
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  ABSTRACT: Reversible logic is very important in low-power circuit design and quantum computing. Though a significant number of works has been done on reversible combinational logic synthesis, only few papers have been published on reversible sequential logic synthesis and per mutative quantum automata. The reported works on reversible sequential logic discuss designs of reversible flip-flops and suggest synthesizing reversible sequential circuits by replacing the flip-flops and combinational parts of traditional sequential circuit designs by their reversible counterparts. In this paper, we discuss direct design of reversible synchronous counters based on positive polarity Reed-Muller expressions. Design results show that the direct design method is more efficient than the replacement method. The method can be also applied to per mutative quantum automata that have quantum memories external to the circuit.
  Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on; 06/2011
• Source

  Available from: tkk.fi

  Conference Proceeding: Answer Set Programming: A Declarative Approach to Solving Challenging Search Problems

  I. Niemelä
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  ABSTRACT: Answer Set Programming (ASP) is a declarative programming paradigm targeted to solving search problems. The basic idea of ASP is similar to, for example, SAT-based planning or constraint satisfaction problems but ASP provides a more powerful knowledge representation language for effective problem encoding. A number of successful ASP systems have already been developed and applied in a large range of areas. The talk explains the theoretical underpinnings of ASP, introduces the answer set programming paradigm, outlines computational techniques used in current ASP solvers, and discusses some interesting applications of the approach.
  Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on; 06/2011
• Conference Proceeding: Recognition of Blurred Images Using Multilayer Neural Network Based on Multi-valued Neurons

  I. Aizenberg, S. Alexander, J. Jackson
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  ABSTRACT: In this paper, we consider a problem of blurred image recognition using a multilayer neural network based on multi-valued neurons (MLMVN). Recognition of blurred images is a challenging problem because it is difficult or even impossible to find any relevant space of features for solving this problem in the spatial domain. The first crucial point of our approach is the use of the frequency domain as a feature space. Since Fourier phase spectrum of a blurred image remains almost unaffected, at least in the low frequency part, it is possible to use phases corresponding to the lowest frequencies as features for recognition. To preserve the physical nature of phase, it is very important to use a machine learning tool for its analysis that treats the phase properly. MLMVN is based on multi-valued neurons whose inputs and output are located on the unit circle and are determined exactly by phase. This approach makes it possible to recognize even heavily blurred images. Our solution works even for images so degraded they cannot be recognized using traditional image recognition techniques, furthermore, even visually
  Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on; 06/2011
• Conference Proceeding: Multiple-Valued Logic Networks with Regular Structure Obtained from Fast Fourier Transforms on Finite Groups

  R.S. Stankovic, J.T. Astola, C. Moraga
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  ABSTRACT: In this paper, we discuss the Fast Fourier transform (FFT) on finite groups as a useful method in synthesis for regularity. FFT is the algorithm for efficient calculation of the Discrete Fourier transform (DFT) and has been extended to computation of various Fourier-like transforms. The algorithm has a very regular structure that can be easily mapped to technology by replacing nodes in the corresponding flow-graphs by circuit modules performing the operations in the flow-graphs. In this way, networks with highly regular structure for implementing functions from their spectra are derived. Fourier transforms on non-Abelian groups offer additional advantages for reducing the required hardware due to matrix-valued spectral coefficients and the way how such coefficients are used in reconstructing the functions. Methods for optimization of spectral representations of functions on finite groups may be applied to improve networks with regular structure.
  Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on; 06/2011
• Conference Proceeding: A Survey on the Arity Gap

  M. Couceiro, E. Lehtonen, T. Waldhauser
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  ABSTRACT: The arity gap of a function of several variables is defined as the minimum decrease in the number of essential variables when essential variables of the function are identified. We present a brief survey on the research done on the arity gap, from the first studies of this notion up to recent developments.
  Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on; 06/2011
• Conference Proceeding: Notes on the Exclusive Disjunction

  I. Garcia-Honrado, E. Trillas
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  ABSTRACT: This short paper just contains some reflections on the symmetric difference operator translating into an algebraic framework the connective exclusive disjunction, the linguistic either/or. In particular, it tries to find an upper bound for the fuzzy operators generalizing the classical symmetric difference, that is, those to deal with imprecise statements. This search is made throughout the preservation of the inferential schemes of disjunctive syllogism in fuzzy logic. The paper tries to stress the inferential interest of the symmetric difference.
  Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on; 06/2011
• Conference Proceeding: On Equational Definability of Function Classes

  M. Couceiro, E. Lehtonen, T. Waldhauser
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  ABSTRACT: We propose a notion of functional equation for functions of a fixed arity, which is based on a pair of clones. We present necessary conditions for a class of functions to be definable by such equations, and show that for certain choices of clones these conditions are also sufficient.
  Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on; 06/2011
• Conference Proceeding: Ultra Low-Voltage and High-Speed CMOS Full Adder Using Floating-Gates and Multiple-Valued Logic

  Y. Berg
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  ABSTRACT: In this paper we present a novel high speed and ultra low-voltage full adder circuit based on ultra low-voltage semi floating-gate CMOS logic. The full adder circuit contains a high speed ultraslow-voltage carry generator circuit and a multiple-valued intermediate representation of the summation. The full adder is suitable for low-voltage serial full adder design. Simulated data presented is valid for a 90nm TSMC CMOS process.
  Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on; 06/2011
• Conference Proceeding: Quantum Phase Estimation Using Multivalued Logic

  V. Parasa, M. Perkowski
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  ABSTRACT: Quantum phase estimation (QPE) is one of the most important quantum algorithms which is used as a subroutine for other important quantum algorithms like Shor's factoring algorithm, simulation of quantum systems, quantum counting and QFT on arbitrary Zp. In this paper we develop the theoretical framework for the multivalued quantum logic version of the QPE algorithm using d valued qudits and show a quantum circuit to implement QPE with a complexity of O(nlogn) single qudit operations. The multivalued QPE algorithm, when compared to the binary quantum logic version, turns out to be more robust and leads to a significant decrease in the number of qudits required along with drastic improvement in the precision and success probability. We derive the requirements to amplify the probability of success to a value very close to 1 (for a given precision), thereby generalizing the previously obtained result in the binary case. Also, we note that the failure probability of QPE algorithm decreases exponentially as d increases.
  Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on; 06/2011
• Source

  Available from: ijcte.org

  Conference Proceeding: Design of High Performance Quaternary Adders

  P.K.S. Vasundara, K.S. Gurumurthy
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  ABSTRACT: Design of the binary logic circuits is limited by the requirement of the interconnections. A possible solution could be arrived at by using a larger set of signals over the same chip area. Multiple-valued logic (MVL) designs are gaining importance from that perspective. This paper presents two types of multiple-valued full adder circuits, implemented in Multiple-Valued voltage-Mode Logic (MV-VML). First type is designed using one hot encoding and barrel shifter. Second full adder circuit is designed by converting the quaternary logic in to unique code, which enables to implement circuit with reduced hard ware. Sum and carry are processed in two separate blocks, controlled by code generator unit. The design is targeted for the 0.18 μm CMOS technology and verification of the design is done through Synopsis HSPICE and COSMOSCOPE Tools. Area of the designed circuits is less than the corresponding binary circuits and quaternary adders because number of transistors used are less.
  Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on; 06/2011