Microelectronics Journal (MICROELECTRON J )

Publisher: Elsevier


Published since 1969, Microelectronics Journal is an international forum for the dissemination of research into, and applications of, microelectronics. Papers published in Microelectronics Journal have undergone peer review to ensure originality, relevance and timeliness. The journal thus provides a worldwide, regular and comprehensive update on semiconductor technology. Coverage of the journal falls into the two main categories of Circuits and Systems and Physics and Devices. The journal invites research and application papers in all the areas listed below. Papers featuring novel system designs or devices are especially welcomed. The journal also considers comprehensive review/survey papers covering recent developments. The journal's coverage includes, but is not limited to: Circuits and Systems Analogue, digital and RF circuit design methodologies Logic, architectural and system level synthesis Testing, design for testability, built in self-test Area, power and thermal evaluation Co-design, including hardware-software and chip-package Mixed-domain simulation and design Formal verification Application aspects such as signal and image processing, sensor and actuator design, reliability and quality issues, and economic models, are also welcome. Physics and Devices Materials growth science: technology and techniques Physics, properties and characterisation of materials systems Devices and microsystems technology: production and manufacturing Advanced lithography for submicron devices and VLSI microlithography Nanoelectronics and nanoprecision instrumentation Technology and applications of magnetic materials Molecular engineering: molecular materials and self-assembly processes Devices covered include semiconductor devices, optoelectronic devices, micromachined devices, nanodevices and hybrid devices. Papers covering the associated materials, physics, properties, fabrication and manufacturing of these devices are also welcomed. Journal homepages: www.elsevier.nl/locate/mejo www.elsevier.com/locate/mejo www.elsevier.co.jp/locate/mejo

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    Microelectronics journal (Online)
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Publications in this journal

  • [Show abstract] [Hide abstract]
    ABSTRACT: The unique adaptive properties of memory resistors (memristors) are ideal for use in computational architectures. Multiple interconnected memristors demonstrate complicated overall behavior which significantly improves the efficiency of logic operations via massive parallelism. Nowadays, within an ever-growing variety of memristive systems, most of the research has so far focused on the properties of the individual devices; little is known about the extraordinary features of complex memristive networks and their application prospects. The composite characteristics of regular and irregular memristive networks are explored in this work. A generalized concept for the construction of composite memristive systems, efficiently built out of individual memristive devices, is presented. A new type of threshold-dependent programmable memristive switches, presenting different electrical characteristics from their structural elements, is proposed. As an example of the introduced approach, a SPICE simulation-based evaluation of several programmable analog circuits is presented. The proposed circuit design approach constitutes a step forward towards novel memristor-based nanoelectronic computational systems and architectures.
    Microelectronics Journal 09/2014;
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    ABSTRACT: This paper presents the design, the fabrication and the characterization of a planar interleaved micro-transformer with an Yttrium Iron Garnet (YIG) core. The design of this micro-transformer and the manufacturing steps are presented. HFSS software is used for the conception and the simulation of the interleaved magnetic micro-transformer. It is composed of two identical windings. A bottom magnetic core is used to improve the integrated transformer performances. To form the windings, we have used a surface micromachining process. We have also used a negative photoresist (SU-8) as an insulating layer and as support for the fabrication of a bridge to connect the central end of the coils to the ground shield. The micro-transformer have been characterized with impedance meter up to 100 MHz, and completed to 1 GHz using vector network analyzer.
    Microelectronics Journal 07/2014; 45(7):893-897.
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    ABSTRACT: Network-on-chip (NoC) has rapidly become a promising alternative for complex system-on-chip architectures including recent multicore architectures. Additionally, optimizing NoC architectures with respect to different design objectives that are suitable for a particular application domain is crucial for achieving high-performance and energy-efficient customized solutions. Despite the fact that many researches have provided various solutions for different aspects of NoCs design, a comprehensive NoCs system solution has not emerged yet. This paper presents a novel methodology to provide a solution for complex on-chip communication problems to reduce power, latency and area overhead. Our proposed NoC communication architecture is based on setting up virtual source–destination paths between selected pairs of NoCs cores so that the packets belonging to distance nodes in the network can bypass intermediate routers while traveling through these virtual paths. In this scheme, the paths are constructed for an application based on its task-graph at the design time. After that, the run time scheduling mechanism is applied to improve the buffer management, virtual channel and switch allocation schemes and hence, the constructed paths are optimized dynamically. Moreover, in our design the router complexity and its overheads are reduced. Additionally, the suggested router has been implemented on Xilinx Virtex-5 FPGA family. The evaluation results captured by SPLASH-2 benchmark suite reveal that in comparison with the conventional NoC router, the proposed router takes 25% and 53% reduction in latency and energy, respectively besides 3.5% area overhead. Indeed, our experimental results demonstrate a significant reduction in the average packet latency and total power consumption with negligible area overhead.
    Microelectronics Journal 04/2014; 45(4):454–462.
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    ABSTRACT: Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide (SiO2) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt to characterize the analog and RF performance of the high-k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2-D device simulation. The results demonstrates the impact of high-k oxide layer as single and gate stack (GS). The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performance exhibited by the device. The major figures of merit (FOMs) studied in this paper are transconductance (gm), output conductance (gd), transconductance generation factor (gm/ID), early voltage (VEA), intrinsic gain (AV), cut off frequency (fT), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). The effects of downscaling of channel length (L) on analog performance of the proposed devices have also been presented. It has been observed that the performance enhancement of GS configurations (k 1⁄47.5 i.e device D5 in the study) is encouraging as far as the nanoscale DG-MOSFET is concerned. Also it significantly reduces the short channel effects (SCEs). Parameters like DC gain of (91.257 dB, 43.436 dB), nearly ideal values (39.765 V À 1, 39.589 V À 1) of TGF, an early voltage of (2.73 V, 16.897 V), cutoff frequency (294 GHz, 515.5 GHz) and GTFP of (5.14 Â 105 GHz/V, 1.72 Â 105 GHz/V) for two different values of VDS 1⁄40.1 V and 0.5 V respectively are found to be close to ideal values. Analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper i.e. device D5.
    Microelectronics Journal 02/2014; 45(2):144-151.
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    ABSTRACT: Backend dielectric breakdown degrades the reliability of circuits. A methodology to estimate chip lifetime due to backend dielectric breakdown is presented. It incorporates failures due to parallel tracks, the width effect, field enhancement due to line ends, and variation in activity and temperature. Different workloads are considered as well, in order to evaluate aging effects in microprocessors running real-world applications with realistic use conditions.
    Microelectronics Journal 01/2014;
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    ABSTRACT: A 5-bit lumped CMOS step attenuator with low insertion loss and low phase distortion is designed and simulated in this paper. The proposed attenuator is based on lumped switched bridged-T and π structure attenuators, and implemented with 0.18-μm CMOS technology. Different attenuation states are controlled by NMOS switches. The switches in series branches have channel-shunt resistance to minimize the on-resistance without increasing parasitic capacitance. The NMOS switches in shunt branches are body-floated to improve the power handling performance of the proposed attenuator. Each attenuation module has an inductive phase-compensate low-pass network. The attenuator is controlled with a 5-bit digital signal to achieve the maximum attenuation amplitude range of 0–31 dB with 1 dB increase at 3–22 GHz. The root mean square (RMS) amplitude errors for each one of the 32 states are less than 0.53 dB and the RMS insertion phase is less than 6.3° at 3–22 GHz. The insertion loss is 5.5–13 dB, and the input P1 dB is 18.4 dBm at 12.5 GHz.
    Microelectronics Journal 01/2014;
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    ABSTRACT: This paper proposes the use of an FPGA-based fault injection technique, AMUSE, to study the effect of malicious attacks on cryptographic circuits. Originally, AMUSE was devised to analyze the soft error effects (SEU and SET) in digital circuits. However, many of the fault-based attacks used in cryptanalysis produce faults that can be modeled as bit-flip in memory elements or transient pulses in combinational logic, as in faults due to radiation effects. Experimental results provide information that allows the cryptographic circuit designer to detect the weakest areas in order to implement countermeasures at design stage.
    Microelectronics Journal 01/2014;
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    ABSTRACT: A CMOS LC voltage controlled oscillator (VCO) based on current reused topology with low phase noise and low power consumption is presented for IEEE 802.11a (Seller et al. A 10 GHz distributed voltage controlled oscillator for WLAN application in a VLSI 65 nm CMOS process, in: IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 3–5 June, 2007, pp. 115–118.) application. The chip1 is designed with the tail current-shaping technique to obtain the phase noise −116.1 dBc/Hz and power consumption 3.71 mW at the operating frequency 5.2 GHz under supply voltage 1.4 V. The second chip of proposed VCO can achieve power consumption Sub 1 mW and is still able to maintain good phase noise. The current reused and body-biased architecture can reduce power consumption, and better phase noise performance is obtained through raising the Q value. The measurement result of the VCO oscillation frequency range is from 5.082 GHz to 5.958 GHz with tuning range of 15.8%. The measured phase noise is −115.88 dBc/Hz at 1 MHz offset at the operation frequency of 5.815 GHz. and the dc core current consumption is 0.71 mA at a supply voltage of 1.4 V. Its figure of merit (FOM) is −191 dBc/Hz. Two circuits were taped out by TSMC 0.18 μm 1P6M process.
    Microelectronics Journal 01/2014; 45(6):627–633.
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    ABSTRACT: The paper presents an approach for the design of high-voltage (HV) current-controlled switches. HV switch structures, properties, application possibilities as well as ways of merging these switches into structure of HV signal processing components, are discussed. New HV switch structures are specialized and modified for specific applications. The switch applications include voltage switching with minimized current-load imposed on circuitry attached to input and output side of the proposed switches, as well as current switching with minimal or no current load to the current-mode signal-path, in HV power and smart-power integrated systems, like DC/DC converters or output power stages. The switch structures and modes of operation are introduced, simulated and discussed.
    Microelectronics Journal 01/2014;
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    ABSTRACT: Nanoelectronics is a very promising step the world of electronics is taking. It is proved to be more efficient than the microelectronic approaches currently in use, mainly in terms of area and energy management. A Single-Electron Transistor (SET) is capable of confining electrons to sufficiently small dimensions, so that the quantization of both their charge and their energy is easily observable, making the SET's quantum mechanical devices. These features should allow building chips with a number of devices orders of magnitude greater than indicated by the roadmap still respecting area and power consumption restrictions. In this sense, Tera Scale Integrated (TSI) systems can be feasible in the future. A digital module, such as an arithmetic logic unit, completely implemented with SETs has already been proposed and validated by simulation. In this work a completely SET based network-on-chip (NoC) nanoelectronic core is proposed. Furthermore, a simple NoC architecture based on that nanoelectronic core is also evaluated. It is shown that the SET-based NoC has a promising performance considering parameters such as power consumption, area and clock frequency. A simple comparison of mesh NoC chip prototypes is shown.
    Microelectronics Journal 01/2014;
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    ABSTRACT: This paper presents a solution for controlling integrated DC–DC converters with high switching frequency (>20 MHz). The increase of the switching frequency is a trend biased by output filter volume restrictions and integration demand. The control of DC–DC converters operating at high frequency presents an opportunity to speed up the converter response time but also a challenge specially for the control solution, quiescent current and to limit the sensitivity to process and operating conditions for the mixed signal circuits involved. The solution presented in this work relies on separating the duty-cycle into three parts: a load-free value that depends only on the input and output voltages, a transient fast correction contribution, and an accurate compensation for the IR drop that depends on the load current. The load-free portion of the duty-cycle has a compensation of PVT variations and the fast transient part of the duty-cycle uses a non-linear sliding mode control solution. All the analog blocks required for the implementation of the proposed solution are detailed.
    Microelectronics Journal 01/2014;
  • Microelectronics Journal 01/2014;
  • Abhishek Mishra, Kamal Kishor Jha, Manisha Pattanaik
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    ABSTRACT: In this work, we discuss the origin and temperature dependence of various mechanisms behind the flow of leakage current in two topologies of TFET – basic TFET and pocket doped TFET. It is shown that the leakage current of pocket doped TFET shows relatively less variations with change in temperature when compared with MOSFET and basic TFET, and hence they can be deployed in low voltage temperature variation prone applications. But, this advantage of pocket-doped TFET is overshadowed by the huge sensitivity of its ON-state current towards variations in doping concentration at the tunnel junction. Hence, the fabrication of the TFET based circuits requires a negotiation with the yield and cost of the fabrication process. In order to mitigate this issue, we propose a hybrid TFET-CMOS based power gating technique. The hybrid technique utilizes a minimum number of TFETs to reduce the sleep mode leakage current, while enabling a temperature variation tolerant sleep mode at a supply voltage of 0.6 V.
    Microelectronics Journal 01/2014;
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    ABSTRACT: As MOSFETs are scaled down to nanometer feature size, random dopant fluctuation (RDF) severely affects CMOS digital integrated circuits (ICs). This paper proposes compact models for estimation of response time and RDF-induced variability in nanoscale CMOS inverter by solution of differential equation considering both input rise time and gate–drain coupling capacitance. The timing characteristics, including propagation delay, overshooting time and transition time, as well as its variability, are accurately modeled in analytical expressions. The proposed models are verified with HSPICE simulations. Monte Carlo analysis also confirms that the models are simple and effective in different design decisions such as width length ratios, load capacitances and source voltages. The studies show that a 7.59% spread in VT variation due to RDF results in about 5% spread in delay variability for the 65 nm CMOS inverter.
    Microelectronics Journal 01/2014; 45(6):678–682.
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    ABSTRACT: Reversible logic is a computing paradigm in which there is a one to one mapping between the input and the output vectors. Reversible logic gates are implemented in an optical domain as it provides high speed and low energy computations. In the existing literature there are two types of optical mapping of reversible logic gates: (i) based on a semiconductor optical amplifier (SOA) using a Mach–Zehnder interferometer (MZI) switch; (ii) based on linear optical quantum computation (LOQC) using linear optical quantum logic gates. In reversible computing, the NAND logic based reversible gates and design methodologies based on them are widely popular. The NOR logic based reversible gates and design methodologies based on them are still unexplored. In this work, we propose two NOR logic based n-input and n-output reversible gates one of which can be efficiently mapped in optical computing using the Mach–Zehnder interferometer (MZI) while the other one can be mapped efficiently in optical computing using the linear optical quantum gates. The proposed reversible NOR gates work as a corresponding NOR counterpart of NAND logic based Toffoli gates. The proposed optical reversible NOR logic gates can implement the reversible boolean logic functions with a reduced number of linear optical quantum logic gates or reduced optical cost and propagation delay compared to their implementation using existing optical reversible NAND gates. It is illustrated that an optical reversible gate library having both optical Toffoli gate and the proposed optical reversible NOR gate is superior compared to the library containing only the optical Toffoli gate: (i) in terms of number of linear optical quantum gates when implemented using linear optical quantum computing (LOQC), (ii) in terms of optical cost and delay when implemented using the Mach–Zehnder interferometer.
    Microelectronics Journal 01/2014;
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    ABSTRACT: A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S21) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm2. The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S21) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm2.
    Microelectronics Journal 01/2014;

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