Microelectronics Journal (MICROELECTRON J)

Publisher: Elsevier

Journal description

Published since 1969, Microelectronics Journal is an international forum for the dissemination of research into, and applications of, microelectronics. Papers published in Microelectronics Journal have undergone peer review to ensure originality, relevance and timeliness. The journal thus provides a worldwide, regular and comprehensive update on semiconductor technology. Coverage of the journal falls into the two main categories of Circuits and Systems and Physics and Devices. The journal invites research and application papers in all the areas listed below. Papers featuring novel system designs or devices are especially welcomed. The journal also considers comprehensive review/survey papers covering recent developments. The journal's coverage includes, but is not limited to: Circuits and Systems Analogue, digital and RF circuit design methodologies Logic, architectural and system level synthesis Testing, design for testability, built in self-test Area, power and thermal evaluation Co-design, including hardware-software and chip-package Mixed-domain simulation and design Formal verification Application aspects such as signal and image processing, sensor and actuator design, reliability and quality issues, and economic models, are also welcome. Physics and Devices Materials growth science: technology and techniques Physics, properties and characterisation of materials systems Devices and microsystems technology: production and manufacturing Advanced lithography for submicron devices and VLSI microlithography Nanoelectronics and nanoprecision instrumentation Technology and applications of magnetic materials Molecular engineering: molecular materials and self-assembly processes Devices covered include semiconductor devices, optoelectronic devices, micromachined devices, nanodevices and hybrid devices. Papers covering the associated materials, physics, properties, fabrication and manufacturing of these devices are also welcomed. Journal homepages: www.elsevier.nl/locate/mejo www.elsevier.com/locate/mejo www.elsevier.co.jp/locate/mejo

Current impact factor: 0.92

Impact Factor Rankings

2015 Impact Factor Available summer 2015
2013 / 2014 Impact Factor 0.924
2012 Impact Factor 0.912
2011 Impact Factor 0.919
2010 Impact Factor 0.787
2009 Impact Factor 0.778
2008 Impact Factor 0.859
2007 Impact Factor 0.609
2006 Impact Factor 0.651
2005 Impact Factor 0.35
2004 Impact Factor 0.483
2003 Impact Factor 0.565
2002 Impact Factor 0.457
2001 Impact Factor 0.333
2000 Impact Factor 0.608
1999 Impact Factor 0.363
1998 Impact Factor 0.345
1997 Impact Factor 0.227

Impact factor over time

Impact factor

Additional details

5-year impact 0.87
Cited half-life 5.80
Immediacy index 0.13
Eigenfactor 0.01
Article influence 0.26
Website Microelectronics Journal website
Other titles Microelectronics journal (Online)
ISSN 0026-2692
OCLC 39061766
Material type Document, Periodical, Internet resource
Document type Internet Resource, Computer File, Journal / Magazine / Newspaper

Publisher details


  • Pre-print
    • Author can archive a pre-print version
  • Post-print
    • Author can archive a post-print version
  • Conditions
    • Pre-print allowed on any website or open access repository
    • Voluntary deposit by author of authors post-print allowed on authors' personal website, arXiv.org or institutions open scholarly website including Institutional Repository, without embargo, where there is not a policy or mandate
    • Deposit due to Funding Body, Institutional and Governmental policy or mandate only allowed where separate agreement between repository and the publisher exists.
    • Permitted deposit due to Funding Body, Institutional and Governmental policy or mandate, may be required to comply with embargo periods of 12 months to 48 months .
    • Set statement to accompany deposit
    • Published source must be acknowledged
    • Must link to journal home page or articles' DOI
    • Publisher's version/PDF cannot be used
    • Articles in some journals can be made Open Access on payment of additional charge
    • NIH Authors articles will be submitted to PubMed Central after 12 months
    • Publisher last contacted on 18/10/2013
  • Classification
    ​ green

Publications in this journal

  • [Show abstract] [Hide abstract]
    ABSTRACT: Recently reported QCA logical and arithmetic designs have completely disregarded the power consumption issue of the circuits. In this paper, a comprehensive power dissipation analysis as well as a structural analysis over the previously published five-input majority gates is performed. During our experimentations, we found that these designs suffer from high power consumption and also structural weaknesses. Therefore, a new ultra-low power and low-complexity five-input majority gate is proposed. For examining our presented design in large array of QCA structures even parity generators, as instances of logical circuits with different lengths up to 32 bits are presented. The simulation results reveal that our proposed designs have significant improvements in contrast to counterparts from implementation requirements and power consumption aspects. QCADesigner tool is used to evaluate functional correctness of the proposed circuits and power dissipation is evaluated using QCAPro simulator as an accurate power estimator tool.
    Microelectronics Journal 06/2015; 46(6):462-471. DOI:10.1016/j.mejo.2015.03.016
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    ABSTRACT: In this paper, a power laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) on InGaAs is proposed to achieve substantial improvement in breakdown voltage, on-resistance and Baliga׳s figure-of-merit with reduced cell pitch. The proposed LDMOSFET contains two vertical gates which are placed in two separate trenches built in the drift region. The source and drain contacts are taken from the top. The modified device has a planer structure implemented on InGaAs which is suitable for medium voltage power integrated circuits. The performance of proposed device is evaluated using two-dimensional numerical simulations and results are compared with that of the conventional LDMOSFET. The proposed structure considerably reduces the electric field inside the drift region due to reduced-surface field (RESURF) effect even at increased doping concentration leading to improved design trade-off. The proposed device provides 144% higher breakdown voltage, 25% lower specific on-resistance, 8 times improvement in figure-of-merit, and 25% reduction in cell pitch as compared to the conventional device.
    Microelectronics Journal 05/2015; 46(5):404-409. DOI:10.1016/j.mejo.2015.02.007
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    ABSTRACT: It is well known that the memristor hysteresis vanishes if the frequency of its sinusoidal excitation increases. Such a regularity is frequently interpreted as one of the most widely known fingerprints of the memristor. Specifying this fingerprint, the paper yields a new piece of knowledge about the frequency dependence of hysteresis for a constant amplitude of the excitation.
    Microelectronics Journal 04/2015; 46(4):298-300. DOI:10.1016/j.mejo.2015.01.007
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    ABSTRACT: Minimum-energy-driven circuit design is highly required in numerous emerging applications such as mobile electronics, wireless sensor nodes, implantable biomedical devices, etc. Due to high computing capability requirements in such applications, SRAMs play a critical role in energy consumption. This paper presents SRAM energy analysis utilizing multi-threshold (multi-Vth) voltage devices and various circuit techniques for power reduction and performance improvement, and suggests optimal device combinations for energy efficiency improvement. In general, higher-Vth devices are preferred in the cross-coupled latches and the write access transistors for reducing leakage current while lower-Vth devices are desired in the read port for implementing higher performance. However, excessively raised Vth in the write paths, i.e. the cross-coupled latches and the write access transistors, leads to slower write speed than read, quickly nullifying improved energy efficiency. In this work, the energy efficiency improvement of 6.24× is achieved only through an optimal device combination in a commercial 65 nm CMOS technology. Employing power reduction and performance boosting techniques together with the optimal device combination enhances the energy efficiency further up to 33×.
    Microelectronics Journal 03/2015; 46(3):265-272. DOI:10.1016/j.mejo.2014.12.003
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    ABSTRACT: As technology scales down, the amount of process variations increases causing Networks-on-Chip (NoC) links, designed to be identical, to have current and delay variations. Thus, some links may fail to meet design timing or power constraints. Using current and delay variations with design constraints, we estimate link failure probability across NoC links. Modeling results show that the average NoC link failure probability across a 4×4 mesh reaches 3.3% for voltage mode (VM) links and 3.7% for current mode (CM) links at 32 nm. The average NoC link failure probability also increases as the supply voltage decreases or the operating frequency increases. As NoC mesh size scales from 4×4 to 8×8, the link failure probability doubles to 8% for VM links at 22 nm. Topology evaluation shows that for small NoC size, the grid topology outperforms the tree one with lower amount of variation. On the other hand, for relatively large NoC sizes, the hierarchical tree and ring topologies outperform the grid topology with lower amount of variations across the links.
    Microelectronics Journal 03/2015; 46(3):248-257. DOI:10.1016/j.mejo.2015.01.004
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    ABSTRACT: Due to the rapid technology advancement in integrated circuit era, the need for the high computation performance together with increasing complexity and manufacturing costs has raised the demand for high-performance configurable designs; therefore, the Application-Specific Instruction Set Processors (ASIPs) are widely used in SoC design. The automated generation of software tools for ASIPs is a commonly used technique, but the automated hardware model generation is less frequently applied in terms of final RTL implementations. Contrary to this, the final register-transfer level models are usually created, at least partly, manually. This paper presents a novel approach for automated hardware model generation for ASIPs. The new solution is based on a novel abstract ASIP model and a modeling language (Algorithmic Microarchitecture Description Language, AMDL) optimized for this architecture model. The proposed AMDL-based pre-synthesis method is based on a set of pre-defined VHDL implementation schemes, which ensure the qualities of the automatically generated register-transfer level models in terms of resource requirement and operation frequency. The design framework implementing the algorithms required by the synthesis method is also presented.
    Microelectronics Journal 03/2015; 46(3):237-247. DOI:10.1016/j.mejo.2015.01.001
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    ABSTRACT: Existing methods to analyze and optimize on-chip power distribution networks typically focus only on global power network modeled as a two-dimensional mesh. In practice, current is supplied to switching transistors through a local power network at the lower metal layers. The local power network is connected to a global network through a stack of vias. The effect of these vias and the resistance of the local power network are typically ignored when optimizing a power network and placing decoupling capacitors. By modeling the power distribution network as a three-dimensional mesh, the error due to ignoring via and local interconnect resistances is quantified. It is demonstrated that ignoring the local power network and vias can both underestimate (by up to 45%) or overestimate (by up to 50%) the effective resistance of a power distribution network. The error depends upon multiple parameters such as the width of local and global power lines and via resistance. A design space is also generated to indicate the valid width of local and global power lines where the target resistance is satisfied. It is shown that a wider global network can be used to obtain a narrower local network, providing additional flexibility in the physical design process since routability is an important concern at lower metal layers. At high via resistances, however, this approach causes significant increase in the width of a global power network, indicating the growing significance of local power network and vias.
    Microelectronics Journal 03/2015; 46(3):258-264. DOI:10.1016/j.mejo.2014.12.004
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    ABSTRACT: Devices that are compact in design and fabrication continue to draw attention for specific applications that require high performance. A compact elliptic bandpass filter using a cross-coupled topological structure with a hairpin resonator optimised for radar applications is presented in this paper. This work presents the design theory and corresponding semiconductor fabrication processes and describes the chip-on-board packaging method in detail. The proposed design of the bandpass filter can not only reduce the size of the device and result in good RF performance, but the accurate semiconductor fabrication process can also ensure high performance further. In addition, the presented chip-on-board packaging method can greatly enhance the reliability and long-term stability of a microwave device, which rarely introduces RF characteristic interference. The simulated, bare-chip measured and final chip-on-board measured results agreed well, which validated the correctness of the proposed approach.
    Microelectronics Journal 03/2015; 46(3):231-236. DOI:10.1016/j.mejo.2014.12.011
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    ABSTRACT: This paper presents Floating gate MOS (FGMOS) based low-voltage low-power variant of recently proposed active element namely Voltage Differencing Inverting Buffered Amplifier (VDIBA). The proposed configuration operates at lower supply voltage ±0.75 V with the total quiescent power consumption of 1.5 mW at the biasing current of 100 µA. Further the operating frequency of the proposed VDIBA is improved by using the resistive compensation method of bandwidth extension in Operational Transconductance Amplifier (OTA) stage of the block. By using resistive compensation method of bandwidth extension, the bandwidth of OTA stage increases from 92.47 MHz to 220.67 MHz. As an application, proposed FGMOS based VDIBA has been used to realize a novel resistorless voltage mode (VM) universal filter. The proposed universal filter configuration is capable of realizing all the standard filter functions in both inverting and non-inverting forms simultaneously without any matching constraint. Other important features include independently tunable filter parameters, cascadibility and low sensitivity figure. The proposed filter is tunable over the frequency range of 4.1 MHz to 12.9 MHz and is capable of compensating for process, voltage and temperature (PVT) variation. The simulations are performed using SPICE and TSMC 0.18 µm CMOS technology parameters with±0.75 V supply voltage to validate the effectiveness of the proposed circuit.
    Microelectronics Journal 02/2015; 46(2). DOI:10.1016/j.mejo.2014.11.007
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    ABSTRACT: Reconfigurable integrator/differentiator circuits based on the current follower are presented. They are essential for realizing configurable analog blocks (CABs) for field programmable analog arrays (FPAAs). The proposed circuits provide functional reconfigurations and components reuse. These functions provide flexibility in the area of filter design within CAB architectures. Circuits based on current follower have the potential to operate at higher frequency ranges and offer improved linearity over their counterparts based on the operational amplifier and transconductance amplifier, respectively. No switches are used in a signal path in order to avoid degrading the frequency response of the proposed circuits. A CMOS current follower realization compatible with implementation of the proposed designs is adopted. Experimental results obtained from a standard 0.35 µm CMOS process are provided.
    Microelectronics Journal 02/2015; 46(2). DOI:10.1016/j.mejo.2014.12.001
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    ABSTRACT: In this work, a tri-band (Band 39: 1880–1920 MHz, Band 40: 2300–2400 MHz, and Band 38: 2570–2620 MHz), 2-receiver (RX) multiple-in-multiple-out (MIMO), 1-transmitter (TX) TD-LTE (Time Division Long Term Evolution) CMOS transceiver is presented and fabricated in 0.13-μm CMOS technology. The continuous-time delta–sigma A/D converters (CT ΔΣ ADCs) are directly coupled to the RX front-end outputs to achieve low power. With proper gain allocation and a novel carrier leakage calibration, the TX section ensures at least –40 dBc carrier leakage suppression over 86-dB gain range. The transceiver dissipates maximum 171 mW at 2-RX MIMO mode and 183 mW at 1-TX maximum gain mode. To the best of our knowledge, this is the first research paper on fully integrated commercial TD-LTE transceiver.
    Microelectronics Journal 01/2015; DOI:10.1016/j.mejo.2014.10.005
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    ABSTRACT: In the application for the space radiation environment, NML circuits face a reliability challenge mainly from their CMOS peripheral circuits, suffering from single event effects (SEE). An on-chip readout interface circuit (RIC) for NML circuit is designed based on dual-barrier magnetic tunnel junction (DB-MTJ). The sensitive nodes to SEE in RIC are analyzed. The SEU required critical charge in RIC is described. The impacts of energetic particle hitting time and technology node on the critical charge are studied. As the technology node scales down, the critical charge will significantly decrease. Two efficient hardening technologies for RIC are presented: local transistors׳ size and symmetrical load capacitances. By increasing local transistors׳ size or decreasing the load capacitance, the critical charge will be improved, which enhances the immunity to SEE.
    Microelectronics Journal 01/2015; DOI:10.1016/j.mejo.2014.09.014
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    ABSTRACT: This paper presents a compact, reliable 1.2 V low-power rail-to-rail class AB operational amplifier (OpAmp) suitable for integrated battery powered systems which require rail-to-rail input/output swing and high slew-rate while maintaining low power consumption. The OpAmp, fabricated in a standard 0.18 μm CMOS technology, exhibits 86 dB open loop gain and 97 dB CMRR. Experimental measurements prove its correct functionality operating with 1.2 V single supply, performing very competitive characteristics compared with other similar amplifiers reported in the literature. It has rail-to-rail input/output operation, 5 MHz unity gain frequency and a 3.15 V/μs slew-rate for a capacitive load of 100 pF, with a power consumption of 99 μW.
    Microelectronics Journal 01/2015; DOI:10.1016/j.mejo.2014.10.011
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    ABSTRACT: In this work a simple all MOS voltage reference circuit has been proposed. To obtain reference output voltage, the thermal compensation has been generated by using a series composite NMOSTs. The voltage reference circuit has been fabricated in a standard 0.18 μm CMOS technology. The proposed circuit is capable of working for the supply voltage ranging from 1.25 V to 2 V. The maximum power dissipation of the proposed circuit is 0.48 μW at the supply voltage of 2 V. The measurement has been performed over a set of 10 samples. It resulted in the mean temperature coefficient (TC) of 19.302 ppm/°C for the temperature range of −40 °C to 85 °C. The measured mean line sensitivity is 2.217 mV/V for the supply voltage ranging from 1.25 V to 2 V at the room temperature. The measured mean power supply rejection ratio at 10 Hz and 1 MHz is −55.31 dB and −16.67 dB respectively for the supply voltage of 1.8 V. Moreover, the measured mean noise density without any filtering capacitor at 100 Hz and 100 kHz are and respectively. Due to its simple circuit implementation, the active area of the circuit is 0.0077 mm2.
    Microelectronics Journal 01/2015; DOI:10.1016/j.mejo.2014.09.015
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    ABSTRACT: A low-distortion feed-forward MASH24b-24b sigma–delta analog-to-digital converter (ADC) for wireless local area network (WLAN) applications was presented. The converter exhibits improved performances than the ADCs which have been presented to date by adding a feedback factor in the second stage and employing a 2nd-order noise-shaping dynamic element matching (DEM) scheme. The feedback factor induces a zero in the noise transfer function (NTF) and therefore improves the in-band signal to noise and distortion ratio (SNDR) of the modulator. The mismatch-shaping DEM was introduced and applied to the 4-bit DACs in this paper to improve the resolution and linearity of the ADC. Fabricated in a 0.18 μm CMOS process with single 1.8 V supply voltage, the converter achieves a peak SNDR of 85.4 dB over a 10 MHz bandwidth which implies an effective number of bits (ENOB) of 13.90-bit. The spurious free dynamic range (SFDR) is –94 dB for a 1.25 MHz@–6dBFS input signal at 160 MHz sampling frequency. The occupied area is 0.44 mm2 and dissipation power 23.4 mW.
    Microelectronics Journal 01/2015; DOI:10.1016/j.mejo.2014.10.004
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    ABSTRACT: A high switching frequency voltage-mode buck converter with fast voltage-tracking speed, wide output range and PWM/PSM control strategy for radio frequency (RF) power amplifiers (PAs) has been proposed. To achieve the fast voltage-tracking speed, the maximum charging and discharging current control method has been used, and the filter inductor and capacitor values are reduced. A novel compensated error amplifier (EA) is presented to realize the wide output range. The investigated converter has been fabricated with GF 0.35 μm CMOS process and can operate at 5 MHz with the output voltage range from 0.6 V to 3.4 V. The experimental results show that the voltage-tracking speed can achieve 8.8 μs/V for up-tracking and 6 μs/V for down-tracking. Besides, the recovery time is less than 8 μs when the load change step is 400 mA.
    Microelectronics Journal 01/2015; DOI:10.1016/j.mejo.2014.11.002
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    ABSTRACT: This paper presents two novel low-voltage level shifter designs: one based on cross-coupled PMOS transistors and the other using current mirror structure. These two level shifters are designed to address the problems of the existing state-of-the-art level shifters. Simulation at 65 nm shows that both of the proposed level shifters achieve significantly better performance (up to 12×) and energy consumption (up to 8×) than the state-of-the-art level shifters with similar or less area consumption while operating from near-threshold to super-threshold region, making them optimal for level shifting in low-power systems with multiple scalable voltage domains.
    Microelectronics Journal 01/2015; DOI:10.1016/j.mejo.2014.10.009