Microelectronics Journal (MICROELECTRON J)

Publisher: Elsevier

Journal description

Published since 1969, Microelectronics Journal is an international forum for the dissemination of research into, and applications of, microelectronics. Papers published in Microelectronics Journal have undergone peer review to ensure originality, relevance and timeliness. The journal thus provides a worldwide, regular and comprehensive update on semiconductor technology. Coverage of the journal falls into the two main categories of Circuits and Systems and Physics and Devices. The journal invites research and application papers in all the areas listed below. Papers featuring novel system designs or devices are especially welcomed. The journal also considers comprehensive review/survey papers covering recent developments. The journal's coverage includes, but is not limited to: Circuits and Systems Analogue, digital and RF circuit design methodologies Logic, architectural and system level synthesis Testing, design for testability, built in self-test Area, power and thermal evaluation Co-design, including hardware-software and chip-package Mixed-domain simulation and design Formal verification Application aspects such as signal and image processing, sensor and actuator design, reliability and quality issues, and economic models, are also welcome. Physics and Devices Materials growth science: technology and techniques Physics, properties and characterisation of materials systems Devices and microsystems technology: production and manufacturing Advanced lithography for submicron devices and VLSI microlithography Nanoelectronics and nanoprecision instrumentation Technology and applications of magnetic materials Molecular engineering: molecular materials and self-assembly processes Devices covered include semiconductor devices, optoelectronic devices, micromachined devices, nanodevices and hybrid devices. Papers covering the associated materials, physics, properties, fabrication and manufacturing of these devices are also welcomed. Journal homepages: www.elsevier.nl/locate/mejo www.elsevier.com/locate/mejo www.elsevier.co.jp/locate/mejo

Current impact factor: 0.92

Impact Factor Rankings

2015 Impact Factor Available summer 2015
2013 / 2014 Impact Factor 0.924
2012 Impact Factor 0.912
2011 Impact Factor 0.919
2010 Impact Factor 0.787
2009 Impact Factor 0.778
2008 Impact Factor 0.859
2007 Impact Factor 0.609
2006 Impact Factor 0.651
2005 Impact Factor 0.35
2004 Impact Factor 0.483
2003 Impact Factor 0.565
2002 Impact Factor 0.457
2001 Impact Factor 0.333
2000 Impact Factor 0.608
1999 Impact Factor 0.363
1998 Impact Factor 0.345
1997 Impact Factor 0.227

Impact factor over time

Impact factor

Additional details

5-year impact 0.87
Cited half-life 5.80
Immediacy index 0.13
Eigenfactor 0.01
Article influence 0.26
Website Microelectronics Journal website
Other titles Microelectronics journal (Online)
ISSN 0026-2692
OCLC 39061766
Material type Document, Periodical, Internet resource
Document type Internet Resource, Computer File, Journal / Magazine / Newspaper

Publisher details


  • Pre-print
    • Author can archive a pre-print version
  • Post-print
    • Author can archive a post-print version
  • Conditions
    • Pre-print allowed on any website or open access repository
    • Voluntary deposit by author of authors post-print allowed on authors' personal website, arXiv.org or institutions open scholarly website including Institutional Repository, without embargo, where there is not a policy or mandate
    • Deposit due to Funding Body, Institutional and Governmental policy or mandate only allowed where separate agreement between repository and the publisher exists.
    • Permitted deposit due to Funding Body, Institutional and Governmental policy or mandate, may be required to comply with embargo periods of 12 months to 48 months .
    • Set statement to accompany deposit
    • Published source must be acknowledged
    • Must link to journal home page or articles' DOI
    • Publisher's version/PDF cannot be used
    • Articles in some journals can be made Open Access on payment of additional charge
    • NIH Authors articles will be submitted to PubMed Central after 12 months
    • Publisher last contacted on 18/10/2013
  • Classification
    ​ green

Publications in this journal

  • [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, a simple structure for short channel junction-less double gate (JLDG) MOSFET is proposed. Further expression for surface potential of JLDG has been derived using 2D Poisson׳s equation. Based on the proposed analytical model for surface potential distribution along channel thickness and channel length is derived. The proposed junction-less MOSFET has no p-n junction as the doping of channel is same to that of Source/Drain region. The analytical model is compared with numerical solution using ATLAS device simulator. The result shows the variation of channel potential with channel length, channel thickness, doping concentration and applied gate bias. Further, in this paper the analog performance and RF figure of merits (FOMs) have been investigated. The purpose of this research is to provide a physical explanation for improved analog and RF performance exhibited by the device. In this paper major FOMs such as trans-conductance (gm), output conductance (gd), early voltage (VEA), intrinsic gain (AV), trans-conductance generation factor (TGF), cut-off frequency (fT), trans-conductance frequency product (TFP), gain frequency product (GFP), gain trans-conductance frequency product (GTFP) are analyzed. The simulation result shows that the JLDG exhibit a higher trans-conductance, higher cut-off frequency and lower drain conductance.
    Microelectronics Journal 08/2015; 46(10):916–922. DOI:10.1016/j.mejo.2015.07.009
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    ABSTRACT: Most commercial Field Programmable Gate Arrays (FPGAs) have limitations in terms of density, speed, configuration overhead and power consumption mostly due to the use of SRAM cells in Look-Up Tables (LUTs), configuration memory and programmable interconnects. Also, hardwired Application Specific Integrated Circuit (ASIC) blocks designed for high performance arithmetic circuits in FPGA reduce the area available for reconfiguration. In this paper, we propose a novel generalized hybrid CMOS-memristor based architecture using stateful-NOR gates as basic building blocks for implementation of logic functions. These logic functions are implemented on memristor nanocrossbar layers, while the CMOS layer is used for selection and connection of memristors. The proposed pipelined architecture combines the features of ASIC, FPGA and microprocessor based designs. It has high density due to the use of nanocrossbar layer and high throughput especially for arithmetic circuits. The proposed architecture for three input one output logic block is compared with conventional LUT based Configurable Logic Block (CLB) having the same number of inputs and outputs; which shows 1.82 x area saving, 1.57 x speedup and 3.63 x less power consumption. The automation algorithm to implement any logic function using proposed architecture is also presented.
    Microelectronics Journal 06/2015; 46(6):551-562. DOI:10.1016/j.mejo.2015.03.021
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    ABSTRACT: The CMOS based temperature detection circuit has been developed in a standard 180 nm CMOS technology. The proposed temperature sensor senses the temperature in terms of the duty cycle in the temperature range of −30 °C to +70 °C. The circuit is divided into three parts, the sensor core, the subtractor and the pulse width modulator. The sensor core consists of two individual circuits which generates voltages proportional (PTAT) and complementary (CTAT) to the absolute temperature. The mean temperature inaccuracy (°C) of PTAT generator is −0.15 °C to +0.35 °C. Similarly, CTAT generator has mean temperature accuracy of ±1 °C. To increase thermal responsivity, the CTAT voltage is subtracted from the PTAT voltage. The resultant voltage has the thermal responsivity of 6.18 mV/°C with the temperature inaccuracy of ±1.3 °C. A simple pulse width modulator (PWM) has been used to express the temperature in terms of the duty cycle. The measured temperature inaccuracy in the duty cycle is less than ±1.5 °C obtained after performing a single point calibration. The operating voltage of the proposed architecture is 1.80±10% V, with the maximum power consumption of 7.2 μW.
    Microelectronics Journal 06/2015; 46(6):482-489. DOI:10.1016/j.mejo.2015.03.014
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    ABSTRACT: An 8 bit switch-capacitor DAC successive approximation analog to digital converter (SAR-ADC) for sensor-RFID application is presented in this paper. To achieve minimum chip area, maximum simplicity is imposed on capacitive DAC; replacing capacitor bank with only a one switch-capacitor circuit. The regulated dynamic current mirror (RDCM) design is introduced to provide stabilized current. This invariable current from RDCM, charging or discharging the only capacitor in circuit is controlled by pulse width modulated signal to realize switch capacitor DAC. The switch control scheme is built using basic AND gates to generate the control signals for RDCM. Only one capacitor and reduced transistor count in digital part reduces the silicon area occupied by the ADC to only 0.0098 mm2. The converter, designed in GPDK 90 nm CMOS, exhibits maximum sampling frequency of 100 kHz & consumes 6.75 µW at 1 V supply. Calculated signal to noise and distortion ratio (SNDR) at 1 V supply and 100 kS/s is 48.68 dB which relates to ENOB of 7.79 bits. The peak values of differential and integral nonlinearity are found to be +0.70/−0.89 LSB and +1.40/−0.10 LSB respectively. Evaluated figure of merit (FOM) is 3.87×1020, which show that the proposed ADC acquires minimal silicon area and has sufficiently low power consumption compared to its counterparts in RFID applications.
    Microelectronics Journal 06/2015; 46(6):453-461. DOI:10.1016/j.mejo.2015.03.009
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    ABSTRACT: This paper describes a bioamplifier that employs a voltage-controlled-pseudo-resistor to achieve tunable bandwidth and wide operating voltage range for biomedical applications. The versatile pseudo-resistor employed provides ultra-high resistance for ac coupling to cancel the dc offset from electrode-tissue interface. The voltage-controlled-pseudo-resistor consists of serial-connected PMOS transistors working at the subthreshold region and an auto-tuning circuit that makes sure the constant (time-invariant) control-voltage of the pseudo-resistor. This bandwidth-tunable bioamplifier is designed in a 0.18-μm standard CMOS process, achieving a gain of 40.2 dB with 10.35-μW power consumption. The designed chip was also used to develop the proof-of-concept prototype. An operation bandwidth of 9.5 kHz, input-referred noise of 5.2 from 6.3 Hz to 9.5 kHz and 5.54 from 250 Hz to 9.5 kHz, and a tunable cutoff-frequency from 6.3-600 Hz were demonstrated to prove our design.
    Microelectronics Journal 06/2015; 46(6):472-481. DOI:10.1016/j.mejo.2015.03.013
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    ABSTRACT: In this paper, a power laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) on InGaAs is proposed to achieve substantial improvement in breakdown voltage, on-resistance and Baliga׳s figure-of-merit with reduced cell pitch. The proposed LDMOSFET contains two vertical gates which are placed in two separate trenches built in the drift region. The source and drain contacts are taken from the top. The modified device has a planer structure implemented on InGaAs which is suitable for medium voltage power integrated circuits. The performance of proposed device is evaluated using two-dimensional numerical simulations and results are compared with that of the conventional LDMOSFET. The proposed structure considerably reduces the electric field inside the drift region due to reduced-surface field (RESURF) effect even at increased doping concentration leading to improved design trade-off. The proposed device provides 144% higher breakdown voltage, 25% lower specific on-resistance, 8 times improvement in figure-of-merit, and 25% reduction in cell pitch as compared to the conventional device.
    Microelectronics Journal 05/2015; 46(5):404-409. DOI:10.1016/j.mejo.2015.02.007
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    ABSTRACT: In many theories and applications, generalized models can give a good head start for further research where the implementation of new elements and/or boundary conditions could become quite complex. In this paper the development of a compact thermal model of an infrared sensor will be presented. This thermal model includes not only the thermal resistances and capacitances of the sensor structure itself but the radiative and convective thermal resistances to the ambience and between the sensor plate and the heat source (thermal transfer impedance) which is important when the heat source and the sensor are in close proximity. Limitations and the applicability of the proposed model are also discussed. We also aim to present how the proposed model can be used for other IR sensor structures as well.
    Microelectronics Journal 04/2015; 46(6):543-550. DOI:10.1016/j.mejo.2015.03.024
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    ABSTRACT: Devices that are compact in design and fabrication continue to draw attention for specific applications that require high performance. A compact elliptic bandpass filter using a cross-coupled topological structure with a hairpin resonator optimised for radar applications is presented in this paper. This work presents the design theory and corresponding semiconductor fabrication processes and describes the chip-on-board packaging method in detail. The proposed design of the bandpass filter can not only reduce the size of the device and result in good RF performance, but the accurate semiconductor fabrication process can also ensure high performance further. In addition, the presented chip-on-board packaging method can greatly enhance the reliability and long-term stability of a microwave device, which rarely introduces RF characteristic interference. The simulated, bare-chip measured and final chip-on-board measured results agreed well, which validated the correctness of the proposed approach.
    Microelectronics Journal 03/2015; 46(3):231-236. DOI:10.1016/j.mejo.2014.12.011
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    ABSTRACT: Due to the rapid technology advancement in integrated circuit era, the need for the high computation performance together with increasing complexity and manufacturing costs has raised the demand for high-performance configurable designs; therefore, the Application-Specific Instruction Set Processors (ASIPs) are widely used in SoC design. The automated generation of software tools for ASIPs is a commonly used technique, but the automated hardware model generation is less frequently applied in terms of final RTL implementations. Contrary to this, the final register-transfer level models are usually created, at least partly, manually. This paper presents a novel approach for automated hardware model generation for ASIPs. The new solution is based on a novel abstract ASIP model and a modeling language (Algorithmic Microarchitecture Description Language, AMDL) optimized for this architecture model. The proposed AMDL-based pre-synthesis method is based on a set of pre-defined VHDL implementation schemes, which ensure the qualities of the automatically generated register-transfer level models in terms of resource requirement and operation frequency. The design framework implementing the algorithms required by the synthesis method is also presented.
    Microelectronics Journal 03/2015; 46(3):237-247. DOI:10.1016/j.mejo.2015.01.001
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    ABSTRACT: Existing methods to analyze and optimize on-chip power distribution networks typically focus only on global power network modeled as a two-dimensional mesh. In practice, current is supplied to switching transistors through a local power network at the lower metal layers. The local power network is connected to a global network through a stack of vias. The effect of these vias and the resistance of the local power network are typically ignored when optimizing a power network and placing decoupling capacitors. By modeling the power distribution network as a three-dimensional mesh, the error due to ignoring via and local interconnect resistances is quantified. It is demonstrated that ignoring the local power network and vias can both underestimate (by up to 45%) or overestimate (by up to 50%) the effective resistance of a power distribution network. The error depends upon multiple parameters such as the width of local and global power lines and via resistance. A design space is also generated to indicate the valid width of local and global power lines where the target resistance is satisfied. It is shown that a wider global network can be used to obtain a narrower local network, providing additional flexibility in the physical design process since routability is an important concern at lower metal layers. At high via resistances, however, this approach causes significant increase in the width of a global power network, indicating the growing significance of local power network and vias.
    Microelectronics Journal 03/2015; 46(3):258-264. DOI:10.1016/j.mejo.2014.12.004
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    ABSTRACT: Minimum-energy-driven circuit design is highly required in numerous emerging applications such as mobile electronics, wireless sensor nodes, implantable biomedical devices, etc. Due to high computing capability requirements in such applications, SRAMs play a critical role in energy consumption. This paper presents SRAM energy analysis utilizing multi-threshold (multi-Vth) voltage devices and various circuit techniques for power reduction and performance improvement, and suggests optimal device combinations for energy efficiency improvement. In general, higher-Vth devices are preferred in the cross-coupled latches and the write access transistors for reducing leakage current while lower-Vth devices are desired in the read port for implementing higher performance. However, excessively raised Vth in the write paths, i.e. the cross-coupled latches and the write access transistors, leads to slower write speed than read, quickly nullifying improved energy efficiency. In this work, the energy efficiency improvement of 6.24× is achieved only through an optimal device combination in a commercial 65 nm CMOS technology. Employing power reduction and performance boosting techniques together with the optimal device combination enhances the energy efficiency further up to 33×.
    Microelectronics Journal 03/2015; 46(3):265-272. DOI:10.1016/j.mejo.2014.12.003
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    ABSTRACT: This paper presents Floating gate MOS (FGMOS) based low-voltage low-power variant of recently proposed active element namely Voltage Differencing Inverting Buffered Amplifier (VDIBA). The proposed configuration operates at lower supply voltage ±0.75 V with the total quiescent power consumption of 1.5 mW at the biasing current of 100 µA. Further the operating frequency of the proposed VDIBA is improved by using the resistive compensation method of bandwidth extension in Operational Transconductance Amplifier (OTA) stage of the block. By using resistive compensation method of bandwidth extension, the bandwidth of OTA stage increases from 92.47 MHz to 220.67 MHz. As an application, proposed FGMOS based VDIBA has been used to realize a novel resistorless voltage mode (VM) universal filter. The proposed universal filter configuration is capable of realizing all the standard filter functions in both inverting and non-inverting forms simultaneously without any matching constraint. Other important features include independently tunable filter parameters, cascadibility and low sensitivity figure. The proposed filter is tunable over the frequency range of 4.1 MHz to 12.9 MHz and is capable of compensating for process, voltage and temperature (PVT) variation. The simulations are performed using SPICE and TSMC 0.18 µm CMOS technology parameters with±0.75 V supply voltage to validate the effectiveness of the proposed circuit.
    Microelectronics Journal 02/2015; 46(2). DOI:10.1016/j.mejo.2014.11.007
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    ABSTRACT: Reconfigurable integrator/differentiator circuits based on the current follower are presented. They are essential for realizing configurable analog blocks (CABs) for field programmable analog arrays (FPAAs). The proposed circuits provide functional reconfigurations and components reuse. These functions provide flexibility in the area of filter design within CAB architectures. Circuits based on current follower have the potential to operate at higher frequency ranges and offer improved linearity over their counterparts based on the operational amplifier and transconductance amplifier, respectively. No switches are used in a signal path in order to avoid degrading the frequency response of the proposed circuits. A CMOS current follower realization compatible with implementation of the proposed designs is adopted. Experimental results obtained from a standard 0.35 µm CMOS process are provided.
    Microelectronics Journal 02/2015; 46(2). DOI:10.1016/j.mejo.2014.12.001